From a8fe3f50c35b9abb13b5b4bd66a9cc505b9dadaf Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 8 Mar 2016 16:17:37 +0100 Subject: [PATCH] pipistrello: grow fifos a bit (may make ise happier) --- artiq/gateware/targets/pipistrello.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index f63cec55a..8cd6b22ee 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -151,7 +151,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i), self.rtio_crg.rtiox4_stb) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=256, + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512, ofifo_depth=4)) # the last TTL is used for ClockGen @@ -166,7 +166,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd phy = ttl_simple.Output(platform.request("ttl", i)) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=128)) + rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256)) phy = ttl_simple.Output(platform.request("ext_led", 0)) self.submodules += phy @@ -182,8 +182,8 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd for i in range(4, 8): phy = ttl_simple.Inout(pmod.d[i]) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=8, - ofifo_depth=8)) + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128, + ofifo_depth=128)) self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) @@ -200,7 +200,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd self.submodules += phy self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.Channel.from_phy( - phy, ofifo_depth=8, ififo_depth=8)) + phy, ofifo_depth=128, ififo_depth=128)) self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels) self.config["DDS_CHANNEL_COUNT"] = 8 @@ -210,7 +210,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd phy = dds.AD9858(dds_pins, 8) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, - ofifo_depth=256, + ofifo_depth=512, ififo_depth=4)) self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)