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compiler/ir: create machine code from kernel statements

This commit is contained in:
Sebastien Bourdeauducq 2014-07-05 22:44:54 +02:00
parent d804f1199e
commit a8ef4d8b91
1 changed files with 10 additions and 51 deletions
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61
artiq/compiler/ir.py
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@ -1,6 +1,7 @@
import ast import ast
from llvm import core as lc from llvm import core as lc
from llvm import passes as lp
class _Namespace: class _Namespace:
def __init__(self, function): def __init__(self, function):
@ -120,42 +121,17 @@ def _emit_statements(env, builder, ns, stmts):
else: else:
raise NotImplementedError raise NotImplementedError
def _emit_function_def(env, module, node): def get_runtime_binary(env, stmts):
function_type = lc.Type.function(lc.Type.int(), [lc.Type.int()]*len(node.args.args)) module = lc.Module.new("main")
function = module.add_function(function_type, node.name) env.set_module(module)
function_type = lc.Type.function(lc.Type.void(), [])
function = module.add_function(function_type, "run")
bb = function.append_basic_block("entry") bb = function.append_basic_block("entry")
builder = lc.Builder.new(bb) builder = lc.Builder.new(bb)
ns = _Namespace(function) ns = _Namespace(function)
for ast_arg, llvm_arg in zip(node.args.args, function.args): _emit_statements(env, builder, ns, stmts)
llvm_arg.name = ast_arg.arg builder.ret_void()
ns.store(builder, llvm_arg, ast_arg.arg)
_emit_statements(env, builder, ns, node.body)
if __name__ == "__main__":
from llvm import target as lt
from llvm import passes as lp
import subprocess
from artiq.devices import runtime, corecom_serial
testcode = """
def run(x):
d = 2
prime = 1
while d*d <= x:
if x % d == 0:
prime = 0
d = d + 1
syscall("printint", prime)
return prime
"""
node = ast.parse(testcode)
fdef = node.body[0]
module = lc.Module.new("main")
_emit_function_def(runtime.Environment(module), module, fdef)
pass_manager = lp.PassManager.new() pass_manager = lp.PassManager.new()
pass_manager.add(lp.PASS_MEM2REG) pass_manager.add(lp.PASS_MEM2REG)
@ -165,21 +141,4 @@ def run(x):
pass_manager.add(lp.PASS_SIMPLIFYCFG) pass_manager.add(lp.PASS_SIMPLIFYCFG)
pass_manager.run(module) pass_manager.run(module)
lt.initialize_all() return env.emit_object()
tm = lt.TargetMachine.new(triple="or1k", cpu="generic")
with open("test.out", "wb") as fout:
objfile = tm.emit_object(module)
fout.write(objfile)
print("=========================")
print(" LLVM IR")
print("=========================")
print(module)
print("")
print("=========================")
print(" OR1K ASM")
print("=========================")
subprocess.call("or1k-elf-objdump -d test.out".split())
corecom_serial.CoreCom().run(objfile)