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spi: cross-reference bit ordering and alignment, closes #482

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Robert Jördens 2016-06-15 15:04:04 +02:00
parent 033aa33c9e
commit a8b211f891
1 changed files with 3 additions and 0 deletions
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artiq/coredevice/spi.py
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@ -196,6 +196,7 @@ class SPIMaster:
deasserting ``cs`` in between. Once a transfer completes, deasserting ``cs`` in between. Once a transfer completes,
the previous transfer's read data is available in the the previous transfer's read data is available in the
``data`` register. ``data`` register.
* For bit alignment and bit ordering see :meth:`set_config`.
This method advances the timeline by the duration of the SPI transfer. This method advances the timeline by the duration of the SPI transfer.
If a transfer is to be chained, the timeline needs to be rewound. If a transfer is to be chained, the timeline needs to be rewound.
@ -207,6 +208,8 @@ class SPIMaster:
def read_async(self): def read_async(self):
"""Trigger an asynchronous read from the ``data`` register. """Trigger an asynchronous read from the ``data`` register.
For bit alignment and bit ordering see :meth:`set_config`.
Reads always finish in two cycles. Reads always finish in two cycles.
Every data register read triggered by a :meth:`read_async` Every data register read triggered by a :meth:`read_async`