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rtio/phy/ttl: support 'set sensitivity and sample' command (#218)

This commit is contained in:
Sebastien Bourdeauducq 2016-09-07 15:42:09 +08:00
parent 269cedd782
commit a7dd356d30
2 changed files with 18 additions and 4 deletions
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11
artiq/gateware/rtio/phy/ttl_serdes_generic.py
View File

@ -90,14 +90,21 @@ class Inout(Module):
# Input
sensitivity = Signal(2)
self.sync.rio += If(self.rtlink.o.stb & (self.rtlink.o.address == 2),
sensitivity.eq(self.rtlink.o.data))
sample = Signal()
self.sync.rio += [
sample.eq(0),
If(self.rtlink.o.stb & self.rtlink.o.address[1],
sensitivity.eq(self.rtlink.o.data),
If(self.rtlink.o.address[0], sample.eq(1))
)
]
i = serdes.i[-1]
i_d = Signal()
self.sync.rio_phy += [
i_d.eq(i),
self.rtlink.i.stb.eq(
sample |
(sensitivity[0] & ( i & ~i_d)) |
(sensitivity[1] & (~i & i_d))
),

11
artiq/gateware/rtio/phy/ttl_simple.py
View File

@ -59,8 +59,14 @@ class Inout(Module):
ts.oe.eq(oe_k)
)
]
self.sync.rio += If(self.rtlink.o.stb & (self.rtlink.o.address == 2),
sensitivity.eq(self.rtlink.o.data))
sample = Signal()
self.sync.rio += [
sample.eq(0),
If(self.rtlink.o.stb & self.rtlink.o.address[1],
sensitivity.eq(self.rtlink.o.data),
If(self.rtlink.o.address[0], sample.eq(1))
)
]
i = Signal()
i_d = Signal()
@ -68,6 +74,7 @@ class Inout(Module):
self.sync.rio_phy += i_d.eq(i)
self.comb += [
self.rtlink.i.stb.eq(
sample |
(sensitivity[0] & ( i & ~i_d)) |
(sensitivity[1] & (~i & i_d))
),