From a7bbcdc1ad2841ffd090fbd5b6a02ff01a77b238 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 27 Jun 2015 21:15:17 +0200 Subject: [PATCH] targets/pipistrello: mon -> moninj --- soc/targets/artiq_pipistrello.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py index 5cdf977dc..5d6f900c1 100644 --- a/soc/targets/artiq_pipistrello.py +++ b/soc/targets/artiq_pipistrello.py @@ -60,7 +60,7 @@ class NIST_QC1(BaseSoC, AMPSoC): "rtio": None, # mapped on Wishbone instead "rtio_crg": 13, "kernel_cpu": 14, - "rtio_mon": 15 + "rtio_moninj": 15 } csr_map.update(BaseSoC.csr_map) mem_map = { @@ -130,7 +130,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd clk_freq=125000000) self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width) self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width) - self.submodules.rtio_mon = rtio.MonInj(rtio_channels) + self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) # CPU connections rtio_csrs = self.rtio.get_csrs()