forked from M-Labs/artiq
firmware, sayma: port converter_spi to spi2
* ksupport/nrt_bus * port ad9154, hmc830, hmc7043 * port local_spi and drtio_spi * port kernel_proto libdrtioaux, satman * change sayma_rtm gateware over * add spi2 NRTSPIMaster * remove spi NRTSPIMaster * change sayma device_db * change HMC830 to open mode and explicitly sequence open mode
This commit is contained in:
parent
68278e225d
commit
a7720d05cd
@ -10,9 +10,8 @@ class AD9154:
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self.chip_select = chip_select
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@kernel
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def setup_bus(self, write_div=16, read_div=16):
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self.bus.set_config_mu(0, write_div, read_div)
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self.bus.set_xfer(self.chip_select, 24, 0)
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def setup_bus(self, div=16):
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self.bus.set_config_mu(0, 24, div, self.chip_select)
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@kernel
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def write(self, addr, data):
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@ -21,7 +21,7 @@ __all__ = [
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"SPI_OFFLINE", "SPI_ACTIVE", "SPI_PENDING",
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"SPI_CS_POLARITY", "SPI_CLK_POLARITY", "SPI_CLK_PHASE",
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"SPI_LSB_FIRST", "SPI_HALF_DUPLEX",
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"SPIMaster", "NRTSPIMaster"
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"SPIMaster"
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]
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@ -284,65 +284,3 @@ class SPIMaster:
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rtio_output(now_mu(), self.channel, SPI_CONFIG_ADDR | SPI_RT2WB_READ,
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0)
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return rtio_input_data(self.channel)
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@syscall(flags={"nounwind", "nowrite"})
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def spi_set_config(busno: TInt32, flags: TInt32, write_div: TInt32, read_div: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall(flags={"nounwind", "nowrite"})
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def spi_set_xfer(busno: TInt32, chip_select: TInt32, write_length: TInt32, read_length: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall(flags={"nounwind", "nowrite"})
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def spi_write(busno: TInt32, data: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall(flags={"nounwind", "nowrite"})
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def spi_read(busno: TInt32) -> TInt32:
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raise NotImplementedError("syscall not simulated")
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class NRTSPIMaster:
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"""Core device non-realtime Serial Peripheral Interface (SPI) bus master.
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Owns one non-realtime SPI bus.
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With this driver, SPI transactions and are performed by the CPU without
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involving RTIO.
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Realtime and non-realtime buses are separate and defined at bitstream
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compilation time.
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See :class:`SPIMaster` for a description of the methods.
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"""
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def __init__(self, dmgr, busno=0, core_device="core"):
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self.core = dmgr.get(core_device)
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self.busno = busno
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@kernel
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def set_config_mu(self, flags=0, write_div=6, read_div=6):
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"""Set the ``config`` register.
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Note that the non-realtime SPI cores are usually clocked by the system
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clock and not the RTIO clock. In many cases, the SPI configuration is
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already set by the firmware and you do not need to call this method.
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The offline bit cannot be set using this method.
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The SPI bus is briefly taken offline when this method is called.
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"""
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spi_set_config(self.busno, flags, write_div, read_div)
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@kernel
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def set_xfer(self, chip_select=0, write_length=0, read_length=0):
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spi_set_xfer(self.busno, chip_select, write_length, read_length)
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@kernel
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def write(self, data=0):
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spi_write(self.busno, data)
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@kernel
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def read(self):
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return spi_read(self.busno)
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@ -8,6 +8,7 @@ time is an error.
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"""
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from artiq.language.core import syscall, kernel, portable, now_mu, delay_mu
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from artiq.language.types import TInt32, TNone
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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@ -16,7 +17,7 @@ __all__ = [
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"SPI_OFFLINE", "SPI_END", "SPI_INPUT",
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"SPI_CS_POLARITY", "SPI_CLK_POLARITY", "SPI_CLK_PHASE",
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"SPI_LSB_FIRST", "SPI_HALF_DUPLEX",
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"SPIMaster"
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"SPIMaster", "NRTSPIMaster"
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]
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SPI_DATA_ADDR = 0
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@ -205,3 +206,53 @@ class SPIMaster:
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:return: SPI input data.
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"""
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return rtio_input_data(self.channel)
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@syscall(flags={"nounwind", "nowrite"})
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def spi_set_config(busno: TInt32, flags: TInt32, length: TInt32, div: TInt32, cs: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall(flags={"nounwind", "nowrite"})
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def spi_write(busno: TInt32, data: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall(flags={"nounwind", "nowrite"})
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def spi_read(busno: TInt32) -> TInt32:
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raise NotImplementedError("syscall not simulated")
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class NRTSPIMaster:
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"""Core device non-realtime Serial Peripheral Interface (SPI) bus master.
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Owns one non-realtime SPI bus.
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With this driver, SPI transactions and are performed by the CPU without
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involving RTIO.
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Realtime and non-realtime buses are separate and defined at bitstream
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compilation time.
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See :class:`SPIMaster` for a description of the methods.
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"""
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def __init__(self, dmgr, busno=0, core_device="core"):
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self.core = dmgr.get(core_device)
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self.busno = busno
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@kernel
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def set_config_mu(self, flags=0, length=8, div=6, cs=1):
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"""Set the ``config`` register.
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Note that the non-realtime SPI cores are usually clocked by the system
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clock and not the RTIO clock. In many cases, the SPI configuration is
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already set by the firmware and you do not need to call this method.
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"""
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spi_set_config(self.busno, flags, length, div, cs)
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@kernel
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def write(self, data=0):
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spi_write(self.busno, data)
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@kernel
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def read(self):
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return spi_read(self.busno)
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@ -95,7 +95,7 @@ device_db = {
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"converter_spi": {
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"type": "local",
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"module": "artiq.coredevice.spi",
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"module": "artiq.coredevice.spi2",
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"class": "NRTSPIMaster",
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},
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"ad9154_spi0": {
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@ -112,7 +112,7 @@ device_db = {
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},
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"rconverter_spi": {
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"type": "local",
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"module": "artiq.coredevice.spi",
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"module": "artiq.coredevice.spi2",
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"class": "NRTSPIMaster",
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"arguments": {"busno": 0x010000}
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},
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@ -21,7 +21,7 @@ device_db = {
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"converter_spi": {
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"type": "local",
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"module": "artiq.coredevice.spi",
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"module": "artiq.coredevice.spi2",
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"class": "NRTSPIMaster",
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},
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"ad9154_spi0": {
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@ -118,7 +118,6 @@ static mut API: &'static [(&'static str, *const ())] = &[
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api!(i2c_read = ::nrt_bus::i2c::read),
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api!(spi_set_config = ::nrt_bus::spi::set_config),
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api!(spi_set_xfer = ::nrt_bus::spi::set_xfer),
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api!(spi_write = ::nrt_bus::spi::write),
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api!(spi_read = ::nrt_bus::spi::read),
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];
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@ -50,17 +50,9 @@ pub mod spi {
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use ::recv;
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use kernel_proto::*;
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pub extern fn set_config(busno: i32, flags: i32, write_div: i32, read_div: i32) {
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pub extern fn set_config(busno: i32, flags: i32, length: i32, div: i32, cs: i32) {
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send(&SpiSetConfigRequest { busno: busno as u32, flags: flags as u8,
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write_div: write_div as u8, read_div: read_div as u8 });
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recv!(&SpiBasicReply { succeeded } => if !succeeded {
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raise!("SPIError", "SPI bus could not be accessed");
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});
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}
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pub extern fn set_xfer(busno: i32, chip_select: i32, write_length: i32, read_length: i32) {
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send(&SpiSetXferRequest { busno: busno as u32, chip_select: chip_select as u16,
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write_length: write_length as u8, read_length: read_length as u8 });
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length: length as u8, div: div as u8, cs: cs as u8 });
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recv!(&SpiBasicReply { succeeded } => if !succeeded {
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raise!("SPIError", "SPI bus could not be accessed");
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});
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@ -3,34 +3,33 @@ use ad9154_reg;
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fn spi_setup(dacno: u8) {
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unsafe {
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csr::converter_spi::offline_write(1);
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while csr::converter_spi::idle_read() == 0 {}
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csr::converter_spi::offline_write(0);
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csr::converter_spi::end_write(1);
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csr::converter_spi::cs_polarity_write(0b0001);
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csr::converter_spi::clk_polarity_write(0);
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csr::converter_spi::clk_phase_write(0);
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csr::converter_spi::lsb_first_write(0);
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csr::converter_spi::half_duplex_write(0);
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csr::converter_spi::clk_div_write_write(16);
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csr::converter_spi::clk_div_read_write(16);
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csr::converter_spi::xfer_len_write_write(24);
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csr::converter_spi::xfer_len_read_write(0);
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csr::converter_spi::length_write(24 - 1);
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csr::converter_spi::div_write(16 - 2);
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csr::converter_spi::cs_write(1 << (csr::CONFIG_CONVERTER_SPI_FIRST_AD9154_CS + dacno as u32));
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csr::converter_spi::offline_write(0);
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}
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}
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fn write(addr: u16, data: u8) {
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unsafe {
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csr::converter_spi::data_write_write(
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_write(
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((addr as u32) << 16) | ((data as u32) << 8));
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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while csr::converter_spi::writable_read() == 0 {}
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}
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}
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fn read(addr: u16) -> u8 {
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unsafe {
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write((1 << 15) | addr, 0);
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csr::converter_spi::data_read_read() as u8
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csr::converter_spi::data_read() as u8
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}
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}
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@ -51,16 +51,24 @@ mod hmc830 {
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fn spi_setup() {
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unsafe {
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csr::converter_spi::offline_write(1);
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while csr::converter_spi::idle_read() == 0 {}
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csr::converter_spi::offline_write(0);
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csr::converter_spi::end_write(1);
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csr::converter_spi::cs_polarity_write(0b0001);
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csr::converter_spi::clk_polarity_write(0);
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csr::converter_spi::clk_phase_write(0);
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csr::converter_spi::lsb_first_write(0);
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csr::converter_spi::half_duplex_write(0);
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csr::converter_spi::clk_div_write_write(8);
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csr::converter_spi::clk_div_read_write(8);
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csr::converter_spi::div_write(16 - 2);
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csr::converter_spi::cs_write(1 << csr::CONFIG_CONVERTER_SPI_HMC830_CS);
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csr::converter_spi::offline_write(0);
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// do a dummy cycle with cs still high to ensure Open mode
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// (rising CLK before rising CS)
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csr::converter_spi::length_write(0);
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csr::converter_spi::data_write(0);
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::length_write(31 - 1);
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}
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}
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@ -68,24 +76,17 @@ mod hmc830 {
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let cmd = (0 << 6) | addr;
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let val = ((cmd as u32) << 24) | data;
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unsafe {
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csr::converter_spi::xfer_len_write_write(32);
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csr::converter_spi::xfer_len_read_write(0);
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csr::converter_spi::data_write_write(val << (32-31));
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_write(val << 1);
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while csr::converter_spi::writable_read() == 0 {}
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}
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}
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fn read(addr: u8) -> u32 {
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let cmd = (1 << 6) | addr;
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let val = (cmd as u32) << 24;
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write(addr, 0);
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unsafe {
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csr::converter_spi::xfer_len_write_write(7);
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csr::converter_spi::xfer_len_read_write(25);
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csr::converter_spi::data_write_write(val << (32-31));
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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csr::converter_spi::data_read_read() & 0xffffff
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_read() & 0xffffff
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}
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}
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@ -123,7 +124,7 @@ mod hmc830 {
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mod hmc7043 {
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use board::csr;
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// To do: check which output channels we actually need
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const DAC_CLK_DIV: u32 = 2;
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const FPGA_CLK_DIV: u32 = 8;
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@ -150,16 +151,17 @@ mod hmc7043 {
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fn spi_setup() {
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unsafe {
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csr::converter_spi::offline_write(1);
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while csr::converter_spi::idle_read() == 0 {}
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csr::converter_spi::offline_write(0);
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csr::converter_spi::end_write(1);
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csr::converter_spi::cs_polarity_write(0b0001);
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csr::converter_spi::clk_polarity_write(0);
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csr::converter_spi::clk_phase_write(0);
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csr::converter_spi::lsb_first_write(0);
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csr::converter_spi::half_duplex_write(1);
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csr::converter_spi::clk_div_write_write(8);
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csr::converter_spi::clk_div_read_write(8);
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csr::converter_spi::half_duplex_write(0); // change mid-transaction for reads
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csr::converter_spi::length_write(24 - 1);
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csr::converter_spi::div_write(16 - 2);
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csr::converter_spi::cs_write(1 << csr::CONFIG_CONVERTER_SPI_HMC7043_CS);
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csr::converter_spi::offline_write(0);
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}
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}
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@ -167,24 +169,29 @@ mod hmc7043 {
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let cmd = (0 << 15) | addr;
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let val = ((cmd as u32) << 8) | data as u32;
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unsafe {
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csr::converter_spi::xfer_len_write_write(24);
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csr::converter_spi::xfer_len_read_write(0);
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csr::converter_spi::data_write_write(val << (32-24));
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_write(val << 8);
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while csr::converter_spi::writable_read() == 0 {}
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}
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}
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fn read(addr: u16) -> u8 {
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let cmd = (1 << 15) | addr;
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let val = (cmd as u32) << 8;
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let val = cmd as u32;
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unsafe {
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csr::converter_spi::xfer_len_write_write(16);
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csr::converter_spi::xfer_len_read_write(8);
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csr::converter_spi::data_write_write(val << (32-24));
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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csr::converter_spi::data_read_read() as u8
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::end_write(0);
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csr::converter_spi::length_write(16 - 1);
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csr::converter_spi::data_write(val << 16);
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::end_write(1);
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csr::converter_spi::half_duplex_write(1);
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csr::converter_spi::length_write(8 - 1);
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csr::converter_spi::data_write(0);
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::half_duplex_write(0);
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csr::converter_spi::length_write(24 - 1);
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csr::converter_spi::data_read() as u8
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}
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}
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@ -233,7 +240,7 @@ mod hmc7043 {
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write(channel_base + 0x4, dphase & 0x1f);
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// No analog phase shift on clock channels
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if (channel % 2) == 0 { write(channel_base + 0x7, 0x00); }
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if (channel % 2) == 0 { write(channel_base + 0x7, 0x00); }
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else { write(channel_base + 0x7, 0x01); }
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write(channel_base + 0x8, 0x08)
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@ -245,6 +252,7 @@ mod hmc7043 {
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pub fn init() -> Result<(), &'static str> {
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clock_mux::init();
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/* must be the first SPI init because of HMC830 SPI mode selection */
|
||||
hmc830::init()?;
|
||||
hmc7043::init()
|
||||
}
|
||||
|
@ -2,33 +2,24 @@
|
||||
mod imp {
|
||||
use board::csr;
|
||||
|
||||
pub fn set_config(busno: u8, flags: u8, write_div: u8, read_div: u8) -> Result<(), ()> {
|
||||
pub fn set_config(busno: u8, flags: u8, length: u8, div: u8, cs: u8) -> Result<(), ()> {
|
||||
if busno != 0 {
|
||||
return Err(())
|
||||
}
|
||||
unsafe {
|
||||
csr::converter_spi::offline_write(1);
|
||||
csr::converter_spi::cs_polarity_write(flags >> 3 & 1);
|
||||
while csr::converter_spi::idle_read() == 0 {}
|
||||
csr::converter_spi::offline_write(flags >> 0 & 1);
|
||||
csr::converter_spi::end_write(flags >> 1 & 1);
|
||||
/* input (in RTIO): flags >> 2 & 1 */
|
||||
/* cs_polarity is a mask in the CSR interface */
|
||||
csr::converter_spi::cs_polarity_write(0xff & (flags >> 3 & 1));
|
||||
csr::converter_spi::clk_polarity_write(flags >> 4 & 1);
|
||||
csr::converter_spi::clk_phase_write(flags >> 5 & 1);
|
||||
csr::converter_spi::lsb_first_write(flags >> 6 & 1);
|
||||
csr::converter_spi::half_duplex_write(flags >> 7 & 1);
|
||||
csr::converter_spi::clk_div_write_write(write_div);
|
||||
csr::converter_spi::clk_div_read_write(read_div);
|
||||
csr::converter_spi::offline_write(0);
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn set_xfer(busno: u8, chip_select: u16, write_length: u8, read_length: u8)
|
||||
-> Result<(), ()> {
|
||||
if busno != 0 {
|
||||
return Err(())
|
||||
}
|
||||
unsafe {
|
||||
csr::converter_spi::cs_write(chip_select as _);
|
||||
csr::converter_spi::xfer_len_write_write(write_length);
|
||||
csr::converter_spi::xfer_len_read_write(read_length);
|
||||
csr::converter_spi::length_write(length - 1);
|
||||
csr::converter_spi::div_write(div - 2);
|
||||
csr::converter_spi::cs_write(cs);
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
@ -38,9 +29,9 @@ mod imp {
|
||||
return Err(())
|
||||
}
|
||||
unsafe {
|
||||
csr::converter_spi::data_write_write(data);
|
||||
while csr::converter_spi::pending_read() != 0 {}
|
||||
while csr::converter_spi::active_read() != 0 {}
|
||||
while csr::converter_spi::writable_read() == 0 {}
|
||||
csr::converter_spi::data_write(data);
|
||||
while csr::converter_spi::writable_read() == 0 {}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
@ -50,16 +41,14 @@ mod imp {
|
||||
return Err(())
|
||||
}
|
||||
Ok(unsafe {
|
||||
csr::converter_spi::data_read_read()
|
||||
csr::converter_spi::data_read()
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(not(has_converter_spi))]
|
||||
mod imp {
|
||||
pub fn set_config(_busno: u8, _flags: u8, _write_div: u8, _read_div: u8) -> Result<(), ()> { Err(()) }
|
||||
pub fn set_xfer(_busno: u8,_chip_select: u16, _write_length: u8, _read_length: u8)
|
||||
-> Result<(), ()> { Err(()) }
|
||||
pub fn set_config(_busno: u8, _flags: u8, _length: u8, _div: u8, _cs: u8) -> Result<(), ()> { Err(()) }
|
||||
pub fn write(_busno: u8,_data: u32) -> Result<(), ()> { Err(()) }
|
||||
pub fn read(_busno: u8,) -> Result<u32, ()> { Err(()) }
|
||||
}
|
||||
|
@ -41,8 +41,7 @@ pub enum Packet {
|
||||
I2cReadReply { succeeded: bool, data: u8 },
|
||||
I2cBasicReply { succeeded: bool },
|
||||
|
||||
SpiSetConfigRequest { busno: u8, flags: u8, write_div: u8, read_div: u8 },
|
||||
SpiSetXferRequest { busno: u8, chip_select: u16, write_length: u8, read_length: u8 },
|
||||
SpiSetConfigRequest { busno: u8, flags: u8, length: u8, div: u8, cs: u8 },
|
||||
SpiWriteRequest { busno: u8, data: u32 },
|
||||
SpiReadRequest { busno: u8 },
|
||||
SpiReadReply { succeeded: bool, data: u32 },
|
||||
@ -123,15 +122,11 @@ impl Packet {
|
||||
0x90 => Packet::SpiSetConfigRequest {
|
||||
busno: read_u8(reader)?,
|
||||
flags: read_u8(reader)?,
|
||||
write_div: read_u8(reader)?,
|
||||
read_div: read_u8(reader)?
|
||||
},
|
||||
0x91 => Packet::SpiSetXferRequest {
|
||||
busno: read_u8(reader)?,
|
||||
chip_select: read_u16(reader)?,
|
||||
write_length: read_u8(reader)?,
|
||||
read_length: read_u8(reader)?
|
||||
length: read_u8(reader)?,
|
||||
div: read_u8(reader)?,
|
||||
cs: read_u8(reader)?
|
||||
},
|
||||
/* 0x91: was Packet::SpiSetXferRequest */
|
||||
0x92 => Packet::SpiWriteRequest {
|
||||
busno: read_u8(reader)?,
|
||||
data: read_u32(reader)?
|
||||
@ -238,19 +233,13 @@ impl Packet {
|
||||
write_bool(writer, succeeded)?;
|
||||
},
|
||||
|
||||
Packet::SpiSetConfigRequest { busno, flags, write_div, read_div } => {
|
||||
Packet::SpiSetConfigRequest { busno, flags, length, div, cs } => {
|
||||
write_u8(writer, 0x90)?;
|
||||
write_u8(writer, busno)?;
|
||||
write_u8(writer, flags)?;
|
||||
write_u8(writer, write_div)?;
|
||||
write_u8(writer, read_div)?;
|
||||
},
|
||||
Packet::SpiSetXferRequest { busno, chip_select, write_length, read_length } => {
|
||||
write_u8(writer, 0x91)?;
|
||||
write_u8(writer, busno)?;
|
||||
write_u16(writer, chip_select)?;
|
||||
write_u8(writer, write_length)?;
|
||||
write_u8(writer, read_length)?;
|
||||
write_u8(writer, length)?;
|
||||
write_u8(writer, div)?;
|
||||
write_u8(writer, cs)?;
|
||||
},
|
||||
Packet::SpiWriteRequest { busno, data } => {
|
||||
write_u8(writer, 0x92)?;
|
||||
|
@ -85,8 +85,7 @@ pub enum Message<'a> {
|
||||
I2cReadReply { succeeded: bool, data: u8 },
|
||||
I2cBasicReply { succeeded: bool },
|
||||
|
||||
SpiSetConfigRequest { busno: u32, flags: u8, write_div: u8, read_div: u8 },
|
||||
SpiSetXferRequest { busno: u32, chip_select: u16, write_length: u8, read_length: u8 },
|
||||
SpiSetConfigRequest { busno: u32, flags: u8, length: u8, div: u8, cs: u8 },
|
||||
SpiWriteRequest { busno: u32, data: u32 },
|
||||
SpiReadRequest { busno: u32 },
|
||||
SpiReadReply { succeeded: bool, data: u32 },
|
||||
|
@ -194,25 +194,13 @@ mod drtio_spi {
|
||||
}
|
||||
}
|
||||
|
||||
pub fn set_config(nodeno: u8, busno: u8, flags: u8, write_div: u8, read_div: u8) -> Result<(), ()> {
|
||||
pub fn set_config(nodeno: u8, busno: u8, flags: u8, length: u8, div: u8, cs: u8) -> Result<(), ()> {
|
||||
let request = drtioaux::Packet::SpiSetConfigRequest {
|
||||
busno: busno,
|
||||
flags: flags,
|
||||
write_div: write_div,
|
||||
read_div: read_div
|
||||
};
|
||||
if drtioaux::hw::send(nodeno, &request).is_err() {
|
||||
return Err(())
|
||||
}
|
||||
basic_reply(nodeno)
|
||||
}
|
||||
|
||||
pub fn set_xfer(nodeno: u8, busno: u8, chip_select: u16, write_length: u8, read_length: u8) -> Result<(), ()> {
|
||||
let request = drtioaux::Packet::SpiSetXferRequest {
|
||||
busno: busno,
|
||||
chip_select: chip_select,
|
||||
write_length: write_length,
|
||||
read_length: read_length
|
||||
length: length,
|
||||
div: div,
|
||||
cs: cs
|
||||
};
|
||||
if drtioaux::hw::send(nodeno, &request).is_err() {
|
||||
return Err(())
|
||||
@ -255,12 +243,7 @@ mod drtio_spi {
|
||||
#[cfg(not(has_drtio))]
|
||||
mod drtio_spi {
|
||||
pub fn set_config(_nodeno: u8, _busno: u8, _flags: u8,
|
||||
_write_div: u8, _read_div: u8) -> Result<(), ()> {
|
||||
Err(())
|
||||
}
|
||||
|
||||
pub fn set_xfer(_nodeno: u8, _busno: u8, _chip_select: u16,
|
||||
_write_length: u8, _read_length: u8) -> Result<(), ()> {
|
||||
_length: u8, _div: u8, _cs: u8) -> Result<(), ()> {
|
||||
Err(())
|
||||
}
|
||||
|
||||
@ -277,23 +260,13 @@ mod spi {
|
||||
use board_artiq::spi as local_spi;
|
||||
use super::drtio_spi;
|
||||
|
||||
pub fn set_config(busno: u32, flags: u8, write_div: u8, read_div: u8) -> Result<(), ()> {
|
||||
pub fn set_config(busno: u32, flags: u8, length: u8, div: u8, cs: u8) -> Result<(), ()> {
|
||||
let nodeno = (busno >> 16) as u8;
|
||||
let node_busno = busno as u8;
|
||||
if nodeno == 0 {
|
||||
local_spi::set_config(node_busno, flags, write_div, read_div)
|
||||
local_spi::set_config(node_busno, flags, length, div, cs)
|
||||
} else {
|
||||
drtio_spi::set_config(nodeno, node_busno, flags, write_div, read_div)
|
||||
}
|
||||
}
|
||||
|
||||
pub fn set_xfer(busno: u32, chip_select: u16, write_length: u8, read_length: u8) -> Result<(), ()> {
|
||||
let nodeno = (busno >> 16) as u8;
|
||||
let node_busno = busno as u8;
|
||||
if nodeno == 0 {
|
||||
local_spi::set_xfer(node_busno, chip_select, write_length, read_length)
|
||||
} else {
|
||||
drtio_spi::set_xfer(nodeno, node_busno, chip_select, write_length, read_length)
|
||||
drtio_spi::set_config(nodeno, node_busno, flags, length, div, cs)
|
||||
}
|
||||
}
|
||||
|
||||
@ -364,14 +337,10 @@ pub fn process_kern_hwreq(io: &Io, request: &kern::Message) -> io::Result<bool>
|
||||
}
|
||||
}
|
||||
|
||||
&kern::SpiSetConfigRequest { busno, flags, write_div, read_div } => {
|
||||
let succeeded = spi::set_config(busno, flags, write_div, read_div).is_ok();
|
||||
&kern::SpiSetConfigRequest { busno, flags, length, div, cs } => {
|
||||
let succeeded = spi::set_config(busno, flags, length, div, cs).is_ok();
|
||||
kern_send(io, &kern::SpiBasicReply { succeeded: succeeded })
|
||||
},
|
||||
&kern::SpiSetXferRequest { busno, chip_select, write_length, read_length } => {
|
||||
let succeeded = spi::set_xfer(busno, chip_select, write_length, read_length).is_ok();
|
||||
kern_send(io, &kern::SpiBasicReply { succeeded: succeeded })
|
||||
}
|
||||
&kern::SpiWriteRequest { busno, data } => {
|
||||
let succeeded = spi::write(busno, data).is_ok();
|
||||
kern_send(io, &kern::SpiBasicReply { succeeded: succeeded })
|
||||
|
@ -94,6 +94,7 @@ fn startup() {
|
||||
#[cfg(si5324_as_synthesizer)]
|
||||
setup_si5324_as_synthesizer();
|
||||
#[cfg(has_hmc830_7043)]
|
||||
/* must be the first SPI init because of HMC830 SPI mode selection */
|
||||
board_artiq::hmc830_7043::init().expect("cannot initialize HMC830/7043");
|
||||
#[cfg(has_ad9154)]
|
||||
board_artiq::ad9154::init().expect("cannot initialize AD9154");
|
||||
|
@ -144,14 +144,10 @@ fn process_aux_packet(p: &drtioaux::Packet) {
|
||||
};
|
||||
}
|
||||
|
||||
drtioaux::Packet::SpiSetConfigRequest { busno, flags, write_div, read_div } => {
|
||||
let succeeded = spi::set_config(busno, flags, write_div, read_div).is_ok();
|
||||
drtioaux::Packet::SpiSetConfigRequest { busno, flags, length, div, cs } => {
|
||||
let succeeded = spi::set_config(busno, flags, length, div, cs).is_ok();
|
||||
drtioaux::hw::send_link(0, &drtioaux::Packet::SpiBasicReply { succeeded: succeeded }).unwrap();
|
||||
},
|
||||
drtioaux::Packet::SpiSetXferRequest { busno, chip_select, write_length, read_length } => {
|
||||
let succeeded = spi::set_xfer(busno, chip_select, write_length, read_length).is_ok();
|
||||
drtioaux::hw::send_link(0, &drtioaux::Packet::SpiBasicReply { succeeded: succeeded }).unwrap();
|
||||
}
|
||||
drtioaux::Packet::SpiWriteRequest { busno, data } => {
|
||||
let succeeded = spi::write(busno, data).is_ok();
|
||||
drtioaux::hw::send_link(0, &drtioaux::Packet::SpiBasicReply { succeeded: succeeded }).unwrap();
|
||||
@ -226,6 +222,7 @@ fn startup() {
|
||||
serwb::wait_init();
|
||||
|
||||
#[cfg(has_hmc830_7043)]
|
||||
/* must be the first SPI init because of HMC830 SPI mode selection */
|
||||
hmc830_7043::init().expect("cannot initialize HMC830/7043");
|
||||
i2c::init();
|
||||
si5324::setup(&SI5324_SETTINGS).expect("cannot initialize Si5324");
|
||||
|
@ -10,7 +10,7 @@ from migen.build.platforms.sinara import sayma_rtm
|
||||
from misoc.interconnect import wishbone, stream
|
||||
from misoc.interconnect.csr import *
|
||||
from misoc.cores import identifier
|
||||
from misoc.cores import spi
|
||||
from misoc.cores import spi2
|
||||
from misoc.cores import gpio
|
||||
from misoc.integration.wb_slaves import WishboneSlaveManager
|
||||
from misoc.integration.cpu_interface import get_csr_csv
|
||||
@ -140,10 +140,10 @@ class SaymaRTM(Module):
|
||||
platform.request("ad9154_txen", 1).eq(0b11)
|
||||
]
|
||||
|
||||
self.submodules.converter_spi = spi.SPIMaster([
|
||||
self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(
|
||||
platform.request("hmc_spi"),
|
||||
platform.request("ad9154_spi", 0),
|
||||
platform.request("ad9154_spi", 1)])
|
||||
platform.request("ad9154_spi", 1)))
|
||||
csr_devices.append("converter_spi")
|
||||
self.comb += platform.request("hmc7043_reset").eq(0)
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user