From a6ffe9f38dff9dbbf1f84f7bd838d4040fc44990 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 21 Dec 2017 23:08:56 +0800 Subject: [PATCH] drtio: add Sayma top-level designs --- artiq/firmware/runtime/lib.rs | 19 +++ .../targets/sayma_amc_drtio_master.py | 122 ++++++++++++++++++ .../targets/sayma_amc_drtio_satellite.py | 113 ++++++++++++++++ 3 files changed, 254 insertions(+) create mode 100755 artiq/gateware/targets/sayma_amc_drtio_master.py create mode 100755 artiq/gateware/targets/sayma_amc_drtio_satellite.py diff --git a/artiq/firmware/runtime/lib.rs b/artiq/firmware/runtime/lib.rs index d7c4a8154..61d0dba4f 100644 --- a/artiq/firmware/runtime/lib.rs +++ b/artiq/firmware/runtime/lib.rs @@ -77,6 +77,8 @@ fn startup() { #[cfg(has_i2c)] board::i2c::init(); + #[cfg(si5324_free_running)] + setup_si5324_free_running(); #[cfg(has_hmc830_7043)] board::hmc830_7043::init().expect("cannot initialize HMC830/7043"); #[cfg(has_ad9154)] @@ -91,6 +93,23 @@ fn startup() { } } +#[cfg(si5324_free_running)] +fn setup_si5324_free_running() +{ + // 150MHz output (hardcoded) + const SI5324_SETTINGS: board::si5324::FrequencySettings + = board::si5324::FrequencySettings { + n1_hs : 9, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 33732, + n31 : 9370, + n32 : 7139, + bwsel : 3 + }; + board::si5324::setup(&SI5324_SETTINGS).expect("cannot initialize Si5324"); +} + #[cfg(has_ethmac)] fn startup_ethernet() { let hardware_addr; diff --git a/artiq/gateware/targets/sayma_amc_drtio_master.py b/artiq/gateware/targets/sayma_amc_drtio_master.py new file mode 100755 index 000000000..cd1bbc149 --- /dev/null +++ b/artiq/gateware/targets/sayma_amc_drtio_master.py @@ -0,0 +1,122 @@ +#!/usr/bin/env python3 + +import argparse + +from migen import * +from migen.build.generic_platform import * + +from misoc.cores import spi as spi_csr +from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict +from misoc.integration.builder import builder_args, builder_argdict +from misoc.targets.sayma_amc import MiniSoC + +from artiq.gateware.amp import AMPSoC, build_artiq_soc +from artiq.gateware import rtio +from artiq.gateware.rtio.phy import ttl_simple +from artiq.gateware.drtio.transceiver import gth_ultrascale +from artiq.gateware.drtio import DRTIOMaster +from artiq import __version__ as artiq_version + + +class Master(MiniSoC, AMPSoC): + mem_map = { + "cri_con": 0x10000000, + "rtio": 0x20000000, + "rtio_dma": 0x30000000, + "drtio_aux": 0x50000000, + "mailbox": 0x70000000 + } + mem_map.update(MiniSoC.mem_map) + + def __init__(self, **kwargs): + MiniSoC.__init__(self, + cpu_type="or1k", + sdram_controller_type="minicon", + l2_size=128*1024, + ident=artiq_version, + ethmac_nrxslots=4, + ethmac_ntxslots=4, + **kwargs) + AMPSoC.__init__(self) + + platform = self.platform + + # Si5324 used as a free-running oscillator, to avoid dependency on RTM. + self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) + self.csr_devices.append("si5324_rst_n") + i2c = self.platform.request("i2c") + self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) + self.csr_devices.append("i2c") + self.config["I2C_BUS_COUNT"] = 1 + self.config["HAS_SI5324"] = None + self.config["SI5324_FREE_RUNNING"] = None + + self.submodules.transceiver = gth_ultrascale.GTH( + clock_pads=platform.request("si5324_clkout"), + tx_pads=[platform.request("sfp_tx")], + rx_pads=[platform.request("sfp_rx")], + sys_clk_freq=self.clk_freq) + + self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})( + DRTIOMaster(self.transceiver.channels[0])) + self.csr_devices.append("drtio0") + self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, + self.drtio0.aux_controller.bus) + self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) + self.config["HAS_DRTIO"] = None + self.add_csr_group("drtio", ["drtio0"]) + self.add_memory_group("drtio_aux", ["drtio0_aux"]) + + rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq + platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period) + platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period) + platform.add_false_path_constraints( + self.crg.cd_sys.clk, + self.transceiver.txoutclk, self.transceiver.rxoutclk) + + rtio_channels = [] + for i in range(4): + phy = ttl_simple.Output(platform.request("user_led", i)) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + sma_io = platform.request("sma_io", 0) + self.comb += sma_io.direction.eq(1) + phy = ttl_simple.Output(sma_io.level) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + sma_io = platform.request("sma_io", 1) + self.comb += sma_io.direction.eq(0) + phy = ttl_simple.InOut(sma_io.level) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + + self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) + self.csr_devices.append("rtio_moninj") + + self.submodules.rtio_core = rtio.Core(rtio_channels, 3) + self.csr_devices.append("rtio_core") + + self.submodules.rtio = rtio.KernelInitiator() + self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( + rtio.DMA(self.get_native_sdram_if())) + self.register_kernel_cpu_csrdevice("rtio") + self.register_kernel_cpu_csrdevice("rtio_dma") + self.submodules.cri_con = rtio.CRIInterconnectShared( + [self.rtio.cri, self.rtio_dma.cri], + [self.rtio_core.cri, self.drtio0.cri]) + self.register_kernel_cpu_csrdevice("cri_con") + + +def main(): + parser = argparse.ArgumentParser( + description="ARTIQ device binary builder / Sayma DRTIO master") + builder_args(parser) + soc_sdram_args(parser) + args = parser.parse_args() + + soc = Master(**soc_sdram_argdict(args)) + build_artiq_soc(soc, builder_argdict(args)) + + +if __name__ == "__main__": + main() diff --git a/artiq/gateware/targets/sayma_amc_drtio_satellite.py b/artiq/gateware/targets/sayma_amc_drtio_satellite.py new file mode 100755 index 000000000..aecfca2c1 --- /dev/null +++ b/artiq/gateware/targets/sayma_amc_drtio_satellite.py @@ -0,0 +1,113 @@ +#!/usr/bin/env python3 + +import argparse +import os + +from migen import * +from migen.build.generic_platform import * +from misoc.cores import spi as spi_csr +from misoc.cores import gpio +from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict +from misoc.integration.builder import builder_args, builder_argdict +from misoc.targets.sayma_amc import BaseSoC + +from artiq.gateware import rtio +from artiq.gateware.rtio.phy import ttl_simple +from artiq.gateware.drtio.transceiver import gth_ultrascale +from artiq.gateware.drtio import DRTIOSatellite +from artiq import __version__ as artiq_version +from artiq import __artiq_dir__ as artiq_dir + + +class Satellite(BaseSoC): + mem_map = { + "drtio_aux": 0x50000000, + } + mem_map.update(BaseSoC.mem_map) + + def __init__(self, **kwargs): + BaseSoC.__init__(self, + cpu_type="or1k", + sdram_controller_type="minicon", + l2_size=128*1024, + ident=artiq_version, + **kwargs) + + platform = self.platform + + rtio_channels = [] + for i in range(4): + phy = ttl_simple.Output(platform.request("user_led", i)) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + sma_io = platform.request("sma_io", 0) + self.comb += sma_io.direction.eq(1) + phy = ttl_simple.Output(sma_io.level) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + sma_io = platform.request("sma_io", 1) + self.comb += sma_io.direction.eq(0) + phy = ttl_simple.InOut(sma_io.level) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + + self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) + self.csr_devices.append("rtio_moninj") + + self.submodules.transceiver = gth_7series.GTH( + clock_pads=platform.request("si5324_clkout"), + tx_pads=platform.request("sfp_tx"), + rx_pads=platform.request("sfp_rx"), + sys_clk_freq=self.clk_freq) + rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) + self.submodules.rx_synchronizer0 = rx0(gth_ultrascale.RXSynchronizer( + self.transceiver.rtio_clk_freq, initial_phase=180.0)) + self.submodules.drtio0 = rx0(DRTIOSatellite( + self.transceiver.channels[0], rtio_channels, self.rx_synchronizer0)) + self.csr_devices.append("rx_synchronizer0") + self.csr_devices.append("drtio0") + self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, + self.drtio0.aux_controller.bus) + self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) + self.config["HAS_DRTIO"] = None + self.add_csr_group("drtio", ["drtio0"]) + self.add_memory_group("drtio_aux", ["drtio0_aux"]) + + self.config["RTIO_FREQUENCY"] = str(self.transceiver.rtio_clk_freq/1e6) + si5324_clkin = platform.request("si5324_clkin") + self.specials += \ + Instance("OBUFDS", + i_I=ClockSignal("rtio_rx0"), + o_O=si5324_clkin.p, o_OB=si5324_clkin.n + ) + self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) + self.csr_devices.append("si5324_rst_n") + i2c = self.platform.request("i2c") + self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) + self.csr_devices.append("i2c") + self.config["I2C_BUS_COUNT"] = 1 + self.config["HAS_SI5324"] = None + + rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq + platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period) + platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period) + platform.add_false_path_constraints( + self.crg.cd_sys.clk, + self.transceiver.txoutclk, self.transceiver.rxoutclk) + + +def main(): + parser = argparse.ArgumentParser( + description="ARTIQ device binary builder / Sayma DRTIO satellite") + builder_args(parser) + soc_sdram_args(parser) + args = parser.parse_args() + + soc = Satellite(**soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.add_software_package("satman", os.path.join(artiq_dir, "firmware", "satman")) + builder.build() + + +if __name__ == "__main__": + main()