forked from M-Labs/artiq
sayma: enable multilink DRTIO
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parent
c34d00cbc9
commit
a6e29462a8
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@ -294,23 +294,39 @@ class Master(MiniSoC, AMPSoC):
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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self.comb += [
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platform.request("sfp_tx_disable", i).eq(0)
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for i in range(2)
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]
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("si5324_clkout"),
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clock_pads=platform.request("si5324_clkout"),
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data_pads=[platform.request("sfp", 0)],
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data_pads=[platform.request("sfp", i) for i in range(2)],
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sys_clk_freq=self.clk_freq,
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.csr_devices.append("drtio_transceiver")
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self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
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drtio_csr_group = []
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DRTIOMaster(self.drtio_transceiver.channels[0]))
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drtio_memory_group = []
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self.csr_devices.append("drtio0")
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drtio_cri = []
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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for i in range(2):
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self.drtio0.aux_controller.bus)
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core_name = "drtio" + str(i)
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self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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memory_name = "drtio" + str(i) + "_aux"
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drtio_csr_group.append(core_name)
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drtio_memory_group.append(memory_name)
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core = ClockDomainsRenamer({"rtio_rx": "rtio_rx"+str(i)})(
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DRTIOMaster(self.drtio_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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memory_address = self.mem_map["drtio_aux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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core.aux_controller.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", ["drtio0"])
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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self.add_memory_group("drtio_aux", drtio_memory_group)
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rtio_clk_period = 1e9/rtio_clk_freq
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rtio_clk_period = 1e9/rtio_clk_freq
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for gth in self.drtio_transceiver.gths:
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for gth in self.drtio_transceiver.gths:
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@ -349,7 +365,7 @@ class Master(MiniSoC, AMPSoC):
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri, self.drtio0.cri])
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[self.rtio_core.cri] + drtio_cri)
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self.register_kernel_cpu_csrdevice("cri_con")
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self.register_kernel_cpu_csrdevice("cri_con")
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