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firmware/spi: work around cs_polarity semantics 

The semantics differ between the RTIO and CSR interface.
This commit is contained in:
Robert Jördens 2018-02-28 21:00:01 +01:00
parent cc70578f1f
commit a6ae08d8b8
1 changed files with 10 additions and 3 deletions
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13
artiq/firmware/libboard_artiq/spi.rs
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@ -10,9 +10,16 @@ mod imp {
while csr::converter_spi::idle_read() == 0 {} while csr::converter_spi::idle_read() == 0 {}
csr::converter_spi::offline_write(flags >> 0 & 1); csr::converter_spi::offline_write(flags >> 0 & 1);
csr::converter_spi::end_write(flags >> 1 & 1); csr::converter_spi::end_write(flags >> 1 & 1);
/* input (in RTIO): flags >> 2 & 1 */ // input (in RTIO): flags >> 2 & 1
/* cs_polarity is a mask in the CSR interface */ // cs_polarity is a mask in the CSR interface
csr::converter_spi::cs_polarity_write(0xff & (flags >> 3 & 1)); // only affect the bits that are selected
let mut cs_polarity = csr::converter_spi::cs_polarity_read();
if flags >> 3 & 1 != 0 {
cs_polarity |= cs;
} else {
cs_polarity &= !cs;
}
csr::converter_spi::cs_polarity_write(cs_polarity);
csr::converter_spi::clk_polarity_write(flags >> 4 & 1); csr::converter_spi::clk_polarity_write(flags >> 4 & 1);
csr::converter_spi::clk_phase_write(flags >> 5 & 1); csr::converter_spi::clk_phase_write(flags >> 5 & 1);
csr::converter_spi::lsb_first_write(flags >> 6 & 1); csr::converter_spi::lsb_first_write(flags >> 6 & 1);