forked from M-Labs/artiq
sayma: clean up serwb comments
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@ -57,9 +57,6 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
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]
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# AMC/RTM serwb
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# TODO: cleanup (same comments as in sayma_rtm.py)
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# serwb SERDES
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serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=1)
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self.comb += serwb_pll.refclk.eq(self.crg.cd_sys.clk)
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self.submodules += serwb_pll
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@ -80,7 +77,6 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
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serwb_phy.serdes.cd_serwb_serdes.clk,
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serwb_phy.serdes.cd_serwb_serdes_5x.clk)
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# serwb slave
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serwb_core = serwb.core.SERWBCore(serwb_phy, int(self.clk_freq), mode="slave")
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self.submodules += serwb_core
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self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
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@ -69,7 +69,6 @@ CSR_RANGE_SIZE = 0x800
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class SaymaRTM(Module):
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def __init__(self, platform):
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csr_devices = []
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@ -98,10 +97,7 @@ class SaymaRTM(Module):
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csr_devices.append("converter_spi")
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self.comb += platform.request("hmc7043_reset").eq(0)
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# TODO: avoid having a "serdes" clock domain at the top level, rename to "serwb_serdes" or similar.
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# TODO: the above also applies to sayma_amc_standalone.py.
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# serwb SERDES
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# AMC/RTM serwb
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serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=1)
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self.submodules += serwb_pll
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@ -121,7 +117,6 @@ class SaymaRTM(Module):
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serwb_phy.serdes.cd_serwb_serdes.clk,
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serwb_phy.serdes.cd_serwb_serdes_5x.clk)
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# serwb master
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serwb_core = serwb.core.SERWBCore(serwb_phy, int(clk_freq), mode="master")
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self.submodules += serwb_core
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