diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs
index 1dba30034..6c52df3ee 100644
--- a/artiq/firmware/libboard_artiq/hmc830_7043.rs
+++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs
@@ -176,7 +176,7 @@ pub mod hmc7043 {
         (true,  FPGA_CLK_DIV, 0x08),  // 8: GTP_CLK1
         (false, 0,            0x10),  // 9: AMC_MASTER_AUX_CLK
         (false, 0,            0x10),  // 10: RTM_MASTER_AUX_CLK
-        (false, 0,            0x10),  // 11: FPGA_ADC_SYSREF, LVDS
+        (true,  FPGA_CLK_DIV, 0x10),  // 11: FPGA_ADC_SYSREF, LVDS -- repurposed for siphaser
         (false, 0,            0x08),  // 12: ADC1_CLK
         (false, 0,            0x08),  // 13: ADC1_SYSREF
     ];
diff --git a/artiq/firmware/satman/main.rs b/artiq/firmware/satman/main.rs
index e5b527312..7afa21337 100644
--- a/artiq/firmware/satman/main.rs
+++ b/artiq/firmware/satman/main.rs
@@ -278,7 +278,7 @@ pub extern fn main() -> i32 {
     /* must be the first SPI init because of HMC830 SPI mode selection */
     hmc830_7043::init().expect("cannot initialize HMC830/7043");
     #[cfg(has_ad9154)]
-    board_artiq::ad9154::init(SYSREF_PHASE_FPGA, SYSREF_PHASE_DAC);
+    let mut ad9154_initialized = false;
     #[cfg(has_allaki_atts)]
     board_artiq::hmc542::program_all(8/*=4dB*/);
 
@@ -289,6 +289,13 @@ pub extern fn main() -> i32 {
         info!("link is up, switching to recovered clock");
         si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
         si5324::siphaser::calibrate_skew(SIPHASER_PHASE).expect("failed to calibrate skew");
+        #[cfg(has_ad9154)]
+        {
+            if !ad9154_initialized {
+                board_artiq::ad9154::init(SYSREF_PHASE_FPGA, SYSREF_PHASE_DAC);
+                ad9154_initialized = true;
+            }
+        }
         drtioaux::reset(0);
         drtio_reset(false);
         drtio_reset_phy(false);
diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py
index 35eaa5099..7090805ba 100755
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@@ -573,7 +573,7 @@ class Satellite(BaseSoC, RTMCommon):
         self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
         self.submodules.siphaser = SiPhaser7Series(
             si5324_clkin=platform.request("si5324_clkin"),
-            si5324_clkout_fabric=platform.request("si5324_clkout_fabric"))
+            si5324_clkout_fabric=platform.request("adc_sysref"))
         platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]",
             mmcm_ps=self.siphaser.mmcm_ps_output)
         platform.add_false_path_constraints(