forked from M-Labs/artiq
fastlink: fix crc vs data width
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@ -100,7 +100,7 @@ class SerDes(Module):
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),
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If(i == t_frame//2 - 2,
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# inject crc for the last cycle
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Cat(crc_data).eq(self.crc.next),
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Cat(crc_data[-n_crc:]).eq(self.crc.next),
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),
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]
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@ -46,7 +46,7 @@ class Phaser(Module):
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header.we.eq(~self.config.o.address[-1]),
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header.addr.eq(self.config.o.address),
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header.data.eq(self.config.o.data),
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header.type.eq(0), # reserved
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header.type.eq(1), # reserved
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),
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]
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