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fastlink: fix crc vs data width

This commit is contained in:
Robert Jördens 2020-08-23 19:02:39 +00:00
parent 7e584d0da1
commit a27a03ab3c
2 changed files with 2 additions and 2 deletions
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2
artiq/gateware/rtio/phy/fastlink.py
View File

@ -100,7 +100,7 @@ class SerDes(Module):
), ),
If(i == t_frame//2 - 2, If(i == t_frame//2 - 2,
# inject crc for the last cycle # inject crc for the last cycle
Cat(crc_data).eq(self.crc.next), Cat(crc_data[-n_crc:]).eq(self.crc.next),
), ),
] ]

2
artiq/gateware/rtio/phy/phaser.py
View File

@ -46,7 +46,7 @@ class Phaser(Module):
header.we.eq(~self.config.o.address[-1]), header.we.eq(~self.config.o.address[-1]),
header.addr.eq(self.config.o.address), header.addr.eq(self.config.o.address),
header.data.eq(self.config.o.data), header.data.eq(self.config.o.data),
header.type.eq(0), # reserved header.type.eq(1), # reserved
), ),
] ]