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differentiate phaser modes

This commit is contained in:
Robert Jördens 2022-09-02 11:03:23 +00:00
parent 31663556b8
commit a20087848d
4 changed files with 47 additions and 32 deletions

View File

@ -190,7 +190,7 @@ class Phaser:
def __init__(self, dmgr, channel_base, miso_delay=1, tune_fifo_offset=True,
clk_sel=0, sync_dly=0, dac=None, trf0=None, trf1=None,
core_device="core"):
mode="base", core_device="core"):
self.channel_base = channel_base
self.core = dmgr.get(core_device)
# TODO: auto-align miso-delay in phy
@ -230,6 +230,8 @@ class Phaser:
if debug:
print("gw_rev:", gw_rev)
self.core.break_realtime()
is_base = gw_rev == 1
is_miqro = gw_rev == 2
delay(.1*ms) # slack
# allow a few errors during startup and alignment since boot
@ -350,6 +352,7 @@ class Phaser:
channel.set_servo(profile=0, enable=0, hold=1)
if is_base:
# test oscillators and DUC
for i in range(len(channel.oscillator)):
oscillator = channel.oscillator[i]
@ -826,6 +829,7 @@ class PhaserChannel:
self.trf_mmap = TRF372017(trf).get_mmap()
self.oscillator = [PhaserOscillator(self, osc) for osc in range(5)]
self.miqro = Miqro(self)
@kernel
def get_dac_data(self) -> TInt32:
@ -1269,3 +1273,10 @@ class PhaserOscillator:
raise ValueError("amplitude out of bounds")
pow = int32(round(phase*(1 << 16)))
self.set_amplitude_phase_mu(asf, pow, clr)
class Miqro:
def __init__(self, channel):
self.channel = channel
self.base_addr = (self.channel.phaser.channel_base + 1 +
self.channel.index) << 8

View File

@ -559,6 +559,7 @@ class PeripheralManager:
return 1
def process_phaser(self, rtio_offset, peripheral):
mode = peripheral.get("mode", "base")
self.gen("""
device_db["{name}"] = {{
"type": "local",
@ -567,11 +568,14 @@ class PeripheralManager:
"arguments": {{
"channel_base": 0x{channel:06x},
"miso_delay": 1,
"mode": "{mode}"
}}
}}""",
name=self.get_name("phaser"),
mode=mode,
channel=rtio_offset)
return 5
rtio_channels = {"base": 5, "miqro": 3}[mode]
return rtio_channels
def process_hvamp(self, rtio_offset, peripheral):
hvamp_name = self.get_name("hvamp")

View File

@ -709,11 +709,11 @@ class Phaser(_EEM):
) for pol in "pn"]
@classmethod
def add_std(cls, target, eem, mode, iostandard=default_iostandard):
def add_std(cls, target, eem, mode="base", iostandard=default_iostandard):
cls.add_extension(target, eem, iostandard=iostandard)
if mode == "phaser":
phy = phaser.Phaser(
if mode == "base":
phy = phaser.Base(
target.platform.request("phaser{}_ser_p".format(eem)),
target.platform.request("phaser{}_ser_n".format(eem)))
target.submodules += phy

View File

@ -28,7 +28,7 @@ class DDSChannel(Module):
[Cat(i.a, i.clr, i.p) for i in self.dds.i])
class Phaser(Module):
class Base(Module):
def __init__(self, pins, pins_n):
self.rtlink = rtlink.Interface(
rtlink.OInterface(data_width=8, address_width=8,