forked from M-Labs/artiq
Revert "artiq_flash: ignore RTM FPGA"
Naive optimism.
This reverts commit 100bda2582
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parent
100bda2582
commit
a1b8bca1e6
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@ -147,8 +147,9 @@ class ProgrammerSayma(Programmer):
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"adapter_khz 5000",
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"transport select jtag",
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"source [find cpld/xilinx-xc7.cfg]", # tap 0, pld 0
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"set CHIP XCKU040",
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"source [find cpld/xilinx-xcu.cfg]",
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"source [find cpld/xilinx-xcu.cfg]", # tap 1, pld 1
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"target create xcu.proxy testee -chain-position xcu.tap",
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"set XILINX_USER1 0x02",
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@ -158,11 +159,11 @@ class ProgrammerSayma(Programmer):
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]
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self.init()
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def load(self, bitfile):
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self.prog.append("pld load 0 {{{}}}".format(bitfile))
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def load(self, bitfile, pld=1):
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self.prog.append("pld load {} {{{}}}".format(pld, bitfile))
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def proxy(self, proxy_bitfile):
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self.load(proxy_bitfile)
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def proxy(self, proxy_bitfile, pld=1):
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self.load(proxy_bitfile, pld)
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self.prog.append("reset halt")
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def flash_binary(self, flashno, address, filename):
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