From a04bd5a4fd2bf9328c33ab2ec72f37ae65d07f25 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Thu, 8 Mar 2018 15:22:07 +0000 Subject: [PATCH] spi2: xfers take one more cycle until ~busy --- artiq/coredevice/spi2.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/coredevice/spi2.py b/artiq/coredevice/spi2.py index 31e1effa2..d64f1ad17 100644 --- a/artiq/coredevice/spi2.py +++ b/artiq/coredevice/spi2.py @@ -162,7 +162,7 @@ class SPIMaster: raise ValueError("Invalid SPI transfer length") if div > 257 or div < 2: raise ValueError("Invalid SPI clock divider") - self.xfer_duration_mu = (length + 1)*div*self.ref_period_mu + self.xfer_duration_mu = ((length + 1)*div + 1)*self.ref_period_mu rtio_output(now_mu(), self.channel, SPI_CONFIG_ADDR, flags | ((length - 1) << 8) | ((div - 2) << 16) | (cs << 24)) delay_mu(self.ref_period_mu)