forked from M-Labs/artiq
kasli: add SED lanes count option to HW description JSON file (#1745)
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
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@ -20,6 +20,8 @@ Highlights:
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- Exposes upconverter calibration and enabling/disabling of upconverter LO & RF outputs.
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- Exposes upconverter calibration and enabling/disabling of upconverter LO & RF outputs.
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- Add helpers to align Phaser updates to the RTIO timeline (``get_next_frame_mu()``)
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- Add helpers to align Phaser updates to the RTIO timeline (``get_next_frame_mu()``)
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* ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912
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* ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912
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* On Kasli, the number of FIFO lanes in the scalable events dispatcher (SED) can now be configured in
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the JSON hardware description file.
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* New hardware support:
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* New hardware support:
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- HVAMP_8CH 8 channel HV amplifier for Fastino / Zotino
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- HVAMP_8CH 8 channel HV amplifier for Fastino / Zotino
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* ``artiq_ddb_template`` generates edge-counter keys that start with the key of the corresponding
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* ``artiq_ddb_template`` generates edge-counter keys that start with the key of the corresponding
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@ -64,6 +64,13 @@
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"type": "boolean",
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"type": "boolean",
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"default": false
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"default": false
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},
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},
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"sed_lanes": {
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"type": "number",
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"minimum": 1,
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"maximum": 32,
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"default": 8,
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"description": "Number of FIFOs in the SED, must be a power of 2"
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},
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"peripherals": {
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"peripherals": {
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"type": "array",
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"type": "array",
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"items": {
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"items": {
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@ -135,12 +135,12 @@ class StandaloneBase(MiniSoC, AMPSoC):
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self.config["HAS_SI5324"] = None
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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self.config["SI5324_SOFT_RESET"] = None
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def add_rtio(self, rtio_channels):
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def add_rtio(self, rtio_channels, sed_lanes=8):
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self.submodules.rtio_crg = _RTIOCRG(self.platform)
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self.submodules.rtio_crg = _RTIOCRG(self.platform)
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self.csr_devices.append("rtio_crg")
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(self.platform)
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fix_serdes_timing_path(self.platform)
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels, lane_count=sed_lanes)
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self.csr_devices.append("rtio_core")
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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@ -375,13 +375,13 @@ class MasterBase(MiniSoC, AMPSoC):
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self.csr_devices.append("rtio_crg")
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(platform)
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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def add_rtio(self, rtio_channels, sed_lanes=8):
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# Only add MonInj core if there is anything to monitor
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# Only add MonInj core if there is anything to monitor
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if any([len(c.probes) for c in rtio_channels]):
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if any([len(c.probes) for c in rtio_channels]):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels, lane_count=sed_lanes)
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self.csr_devices.append("rtio_core")
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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@ -608,13 +608,13 @@ class SatelliteBase(BaseSoC):
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self.csr_devices.append("rtio_crg")
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(platform)
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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def add_rtio(self, rtio_channels, sed_lanes=8):
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# Only add MonInj core if there is anything to monitor
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# Only add MonInj core if there is anything to monitor
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if any([len(c.probes) for c in rtio_channels]):
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if any([len(c.probes) for c in rtio_channels]):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.csr_devices.append("rtio_moninj")
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels, lane_count=sed_lanes)
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self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
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self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.drtiosat.cri],
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[self.drtiosat.cri],
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@ -57,7 +57,8 @@ class GenericStandalone(StandaloneBase):
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
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if has_grabber:
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if has_grabber:
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self.config["HAS_GRABBER"] = None
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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self.add_csr_group("grabber", self.grabber_csr_group)
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@ -94,7 +95,7 @@ class GenericMaster(MasterBase):
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
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if has_grabber:
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if has_grabber:
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self.config["HAS_GRABBER"] = None
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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self.add_csr_group("grabber", self.grabber_csr_group)
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@ -127,7 +128,7 @@ class GenericSatellite(SatelliteBase):
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
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if has_grabber:
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if has_grabber:
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self.config["HAS_GRABBER"] = None
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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self.add_csr_group("grabber", self.grabber_csr_group)
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