From 9f6b3f6014ca53da669aeb0344195534efebf631 Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Wed, 1 Sep 2021 17:43:41 +0800
Subject: [PATCH] firmware: clarify target triple

The lack of compressed instruction support can be inferred from the target triple, literally.
---
 artiq/firmware/libboard_misoc/lib.rs          |  2 +-
 .../{riscv32imac => riscv32ima}/boot.rs       |  0
 .../{riscv32imac => riscv32ima}/cache.rs      |  0
 .../{riscv32imac => riscv32ima}/mod.rs        |  0
 .../{riscv32imac => riscv32ima}/vectors.S     |  0
 .../firmware/riscv32ima-unknown-none-elf.json | 32 +++++++++++++++++++
 6 files changed, 33 insertions(+), 1 deletion(-)
 rename artiq/firmware/libboard_misoc/{riscv32imac => riscv32ima}/boot.rs (100%)
 rename artiq/firmware/libboard_misoc/{riscv32imac => riscv32ima}/cache.rs (100%)
 rename artiq/firmware/libboard_misoc/{riscv32imac => riscv32ima}/mod.rs (100%)
 rename artiq/firmware/libboard_misoc/{riscv32imac => riscv32ima}/vectors.S (100%)
 create mode 100644 artiq/firmware/riscv32ima-unknown-none-elf.json

diff --git a/artiq/firmware/libboard_misoc/lib.rs b/artiq/firmware/libboard_misoc/lib.rs
index 7057f10f2..729f4d63b 100644
--- a/artiq/firmware/libboard_misoc/lib.rs
+++ b/artiq/firmware/libboard_misoc/lib.rs
@@ -8,7 +8,7 @@ extern crate log;
 extern crate smoltcp;
 
 #[cfg(target_arch = "riscv32")]
-#[path = "riscv32imac/mod.rs"]
+#[path = "riscv32ima/mod.rs"]
 mod arch;
 
 #[cfg(target_arch = "riscv32")]
diff --git a/artiq/firmware/libboard_misoc/riscv32imac/boot.rs b/artiq/firmware/libboard_misoc/riscv32ima/boot.rs
similarity index 100%
rename from artiq/firmware/libboard_misoc/riscv32imac/boot.rs
rename to artiq/firmware/libboard_misoc/riscv32ima/boot.rs
diff --git a/artiq/firmware/libboard_misoc/riscv32imac/cache.rs b/artiq/firmware/libboard_misoc/riscv32ima/cache.rs
similarity index 100%
rename from artiq/firmware/libboard_misoc/riscv32imac/cache.rs
rename to artiq/firmware/libboard_misoc/riscv32ima/cache.rs
diff --git a/artiq/firmware/libboard_misoc/riscv32imac/mod.rs b/artiq/firmware/libboard_misoc/riscv32ima/mod.rs
similarity index 100%
rename from artiq/firmware/libboard_misoc/riscv32imac/mod.rs
rename to artiq/firmware/libboard_misoc/riscv32ima/mod.rs
diff --git a/artiq/firmware/libboard_misoc/riscv32imac/vectors.S b/artiq/firmware/libboard_misoc/riscv32ima/vectors.S
similarity index 100%
rename from artiq/firmware/libboard_misoc/riscv32imac/vectors.S
rename to artiq/firmware/libboard_misoc/riscv32ima/vectors.S
diff --git a/artiq/firmware/riscv32ima-unknown-none-elf.json b/artiq/firmware/riscv32ima-unknown-none-elf.json
new file mode 100644
index 000000000..ddacc0247
--- /dev/null
+++ b/artiq/firmware/riscv32ima-unknown-none-elf.json
@@ -0,0 +1,32 @@
+{
+    "arch": "riscv32",
+    "cpu": "generic-rv32",
+    "data-layout": "e-m:e-p:32:32-i64:64-n32-S128",
+    "eh-frame-header": false,
+    "emit-debug-gdb-scripts": false,
+    "executables": true,
+    "features": "+m,+a,-c",
+    "is-builtin": false,
+    "linker": "rust-lld",
+    "linker-flavor": "ld.lld",
+    "llvm-target": "riscv32",
+    "max-atomic-width": 32,
+    "panic-strategy": "unwind",
+    "relocation-model": "static",
+    "target-pointer-width": "32",
+    "unsupported-abis": [
+      "cdecl",
+      "stdcall",
+      "fastcall",
+      "vectorcall",
+      "thiscall",
+      "aapcs",
+      "win64",
+      "sysv64",
+      "ptx-kernel",
+      "msp430-interrupt",
+      "x86-interrupt",
+      "amdgpu-kernel"
+    ]
+  }
+  
\ No newline at end of file