forked from M-Labs/artiq
firmware: clarify target triple
The lack of compressed instruction support can be inferred from the target triple, literally.
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@ -8,7 +8,7 @@ extern crate log;
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extern crate smoltcp;
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#[cfg(target_arch = "riscv32")]
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#[path = "riscv32imac/mod.rs"]
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#[path = "riscv32ima/mod.rs"]
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mod arch;
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#[cfg(target_arch = "riscv32")]
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@ -0,0 +1,32 @@
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{
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"arch": "riscv32",
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"cpu": "generic-rv32",
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"data-layout": "e-m:e-p:32:32-i64:64-n32-S128",
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"eh-frame-header": false,
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"emit-debug-gdb-scripts": false,
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"executables": true,
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"features": "+m,+a,-c",
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"is-builtin": false,
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"linker": "rust-lld",
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"linker-flavor": "ld.lld",
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"llvm-target": "riscv32",
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"max-atomic-width": 32,
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"panic-strategy": "unwind",
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"relocation-model": "static",
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"target-pointer-width": "32",
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"unsupported-abis": [
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"cdecl",
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"stdcall",
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"fastcall",
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"vectorcall",
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"thiscall",
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"aapcs",
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"win64",
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"sysv64",
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"ptx-kernel",
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"msp430-interrupt",
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"x86-interrupt",
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"amdgpu-kernel"
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]
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}
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