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firmware: clarify target triple

The lack of compressed instruction support can be inferred from the target triple, literally.
This commit is contained in:
occheung 2021-09-01 17:43:41 +08:00
parent 9697ec33eb
commit 9f6b3f6014
6 changed files with 33 additions and 1 deletions

View File

@ -8,7 +8,7 @@ extern crate log;
extern crate smoltcp;
#[cfg(target_arch = "riscv32")]
#[path = "riscv32imac/mod.rs"]
#[path = "riscv32ima/mod.rs"]
mod arch;
#[cfg(target_arch = "riscv32")]

View File

@ -0,0 +1,32 @@
{
"arch": "riscv32",
"cpu": "generic-rv32",
"data-layout": "e-m:e-p:32:32-i64:64-n32-S128",
"eh-frame-header": false,
"emit-debug-gdb-scripts": false,
"executables": true,
"features": "+m,+a,-c",
"is-builtin": false,
"linker": "rust-lld",
"linker-flavor": "ld.lld",
"llvm-target": "riscv32",
"max-atomic-width": 32,
"panic-strategy": "unwind",
"relocation-model": "static",
"target-pointer-width": "32",
"unsupported-abis": [
"cdecl",
"stdcall",
"fastcall",
"vectorcall",
"thiscall",
"aapcs",
"win64",
"sysv64",
"ptx-kernel",
"msp430-interrupt",
"x86-interrupt",
"amdgpu-kernel"
]
}