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firmware: implement board::pcr.

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This commit is contained in:
whitequark 2017-10-16 15:29:42 +00:00
parent e1e1f58ba9
commit 9d356ed93b
4 changed files with 55 additions and 0 deletions
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7
artiq/firmware/Cargo.lock generated
View File

@ -17,10 +17,16 @@ dependencies = [
"board 0.0.0",
]
[[package]]
name = "bitflags"
version = "1.0.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
[[package]]
name = "board"
version = "0.0.0"
dependencies = [
"bitflags 1.0.0 (registry+https://github.com/rust-lang/crates.io-index)",
"build_artiq 0.0.0",
"log 0.3.6 (registry+https://github.com/rust-lang/crates.io-index)",
]
@ -211,6 +217,7 @@ version = "0.1.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
[metadata]
"checksum bitflags 1.0.0 (registry+https://github.com/rust-lang/crates.io-index)" = "f5cde24d1b2e2216a726368b2363a273739c91f4e3eb4e0dd12d672d396ad989"
"checksum byteorder 1.0.0 (registry+https://github.com/rust-lang/crates.io-index)" = "c40977b0ee6b9885c9013cd41d9feffdd22deb3bb4dc3a71d901cc7a77de18c8"
"checksum compiler_builtins 0.1.0 (git+https://github.com/rust-lang-nursery/compiler-builtins?rev=631b568)" = "<none>"
"checksum cslice 0.3.0 (registry+https://github.com/rust-lang/crates.io-index)" = "0f8cb7306107e4b10e64994de6d3274bd08996a7c1322a27b86482392f96be0a"

1
artiq/firmware/libboard/Cargo.toml
View File

@ -13,6 +13,7 @@ build_artiq = { path = "../libbuild_artiq" }
[dependencies]
log = { version = "0.3", default-features = false }
bitflags = { version = "1.0" }
[features]
uart_console = []

3
artiq/firmware/libboard/lib.rs
View File

@ -3,6 +3,8 @@
#[macro_use]
extern crate log;
#[macro_use]
extern crate bitflags;
use core::{cmp, ptr, str};
@ -11,6 +13,7 @@ include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/csr.rs"));
pub mod spr;
pub mod irq;
pub mod cache;
pub mod pcr;
pub mod clock;
pub mod uart;
#[cfg(feature = "uart_console")]

44
artiq/firmware/libboard/pcr.rs Normal file
View File

@ -0,0 +1,44 @@
use spr::*;
bitflags! {
pub struct Counters: u32 {
const LA = SPR_PCMR_LA;
const SA = SPR_PCMR_SA;
const IF = SPR_PCMR_IF;
const DCM = SPR_PCMR_DCM;
const ICM = SPR_PCMR_ICM;
const IFS = SPR_PCMR_IFS;
const LSUS = SPR_PCMR_LSUS;
const BS = SPR_PCMR_BS;
const DTLBM = SPR_PCMR_DTLBM;
const ITLBM = SPR_PCMR_ITLBM;
const DDS = SPR_PCMR_DDS;
const INSTRN = Self::IF.bits;
const MEMORY = Self::LA.bits | Self::SA.bits;
const STALL = Self::DCM.bits | Self::ICM.bits | Self::IFS.bits |
Self::LSUS.bits | Self::BS.bits | Self::DDS.bits ;
const MISS = Self::DTLBM.bits | Self::ITLBM.bits ;
}
}
fn is_valid(index: u32) -> bool {
index < 8 && unsafe { mfspr(SPR_PCMR0 + index) } & SPR_PCMR_CP != 0
}
#[inline]
pub fn setup(index: u32, counters: Counters) {
debug_assert!(is_valid(index));
unsafe {
mtspr(SPR_PCMR0 + index, SPR_PCMR_CISM | SPR_PCMR_CIUM | counters.bits);
mtspr(SPR_PCCR0 + index, 0);
}
}
#[inline]
pub fn read(index: u32) -> u32 {
unsafe {
mfspr(SPR_PCCR0 + index)
}
}