forked from M-Labs/artiq
serwb/scrambler: add flow control
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2f8bd022f7
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9d0e8c27ff
@ -11,6 +11,7 @@ def K(x, y):
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@ResetInserter()
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@CEInserter()
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class _Scrambler(Module):
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def __init__(self, n_io, n_state=23, taps=[17, 22]):
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self.i = Signal(n_io)
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@ -38,26 +39,35 @@ class Scrambler(Module):
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if enable:
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# scrambler
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scrambler = _Scrambler(32)
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self.submodules += scrambler
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self.comb += scrambler.i.eq(sink.data)
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self.submodules.scrambler = scrambler = _Scrambler(32)
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# insert K.29.7 as sync character
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# every sync_interval cycles
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count = Signal(max=sync_interval)
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self.sync += count.eq(count + 1)
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self.comb += [
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If(count == 0,
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scrambler.reset.eq(1),
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source.stb.eq(1),
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source.k[0].eq(1),
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source.d[:8].eq(K(29, 7))
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).Else(
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sink.ack.eq(source.ack),
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source.stb.eq(sink.stb),
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source.d.eq(scrambler.o)
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self.submodules.fsm = fsm = FSM(reset_state="SYNC")
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fsm.act("SYNC",
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scrambler.reset.eq(1),
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source.stb.eq(1),
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source.k[0].eq(1),
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source.d[:8].eq(K(29, 7)),
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NextValue(count, 0),
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If(source.ack,
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NextState("DATA")
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)
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]
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)
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fsm.act("DATA",
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scrambler.i.eq(sink.data),
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sink.ack.eq(source.ack),
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source.stb.eq(1),
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source.d.eq(scrambler.o),
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If(source.stb & source.ack,
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scrambler.ce.eq(1),
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NextValue(count, count + 1),
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If(count == (sync_interval - 1),
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NextState("SYNC")
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)
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)
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)
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else:
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self.comb += [
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sink.connect(source, omit={"data"}),
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@ -75,8 +85,7 @@ class Descrambler(Module):
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if enable:
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# descrambler
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descrambler = _Scrambler(32)
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self.submodules += descrambler
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self.submodules.descrambler = descrambler = _Scrambler(32)
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self.comb += descrambler.i.eq(sink.d)
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# detect K29.7 and synchronize descrambler
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@ -89,7 +98,10 @@ class Descrambler(Module):
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).Else(
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sink.ack.eq(source.ack),
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source.stb.eq(sink.stb),
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source.data.eq(descrambler.o)
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source.data.eq(descrambler.o),
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If(source.stb & source.ack,
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descrambler.ce.eq(1)
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)
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)
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]
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else:
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