From 9cf8db2f1414bf13abb1a4a8439cb679aca93f61 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 28 Feb 2015 12:37:12 +0100 Subject: [PATCH] adapt code to MiSoC's changes --- soc/targets/artiq_kc705.py | 2 +- soc/targets/artiq_ppro.py | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py index 99d75cb1f..b4b2ae92b 100644 --- a/soc/targets/artiq_kc705.py +++ b/soc/targets/artiq_kc705.py @@ -3,7 +3,7 @@ from migen.bank.description import * from migen.bank import wbgen from mibuild.generic_platform import * -from misoclib import gpio +from misoclib.cpu.peripherals import gpio from targets.kc705 import BaseSoC from artiqlib import rtio, ad9858 diff --git a/soc/targets/artiq_ppro.py b/soc/targets/artiq_ppro.py index c7539e2c2..64c0a370d 100644 --- a/soc/targets/artiq_ppro.py +++ b/soc/targets/artiq_ppro.py @@ -3,7 +3,7 @@ from migen.bank.description import * from migen.bank import wbgen from mibuild.generic_platform import * -from misoclib import gpio +from misoclib.cpu.peripherals import gpio from targets.ppro import BaseSoC from artiqlib import rtio, ad9858 @@ -96,6 +96,7 @@ class ARTIQMiniSoC(BaseSoC): with_test_gen=False, **kwargs): BaseSoC.__init__(self, platform, cpu_type=cpu_type, ramcon_type=ramcon_type, + with_l2=with_l2, **kwargs) platform.add_extension(_tester_io)