embedding: s/kernel_constant_attributes/kernel_invariants/g

Requested in #359.

artiq/compiler/embedding.py

@@ -137,9 +137,9 @@ class ASTSynthesizer:
                     instance_type = types.TInstance("{}.{}".format(typ.__module__, typ.__qualname__),
                                                     OrderedDict())
                     instance_type.attributes['__objectid__'] = builtins.TInt32()
-                    if hasattr(typ, 'kernel_constant_attributes'):
-                        assert isinstance(typ.kernel_constant_attributes, set)
-                        instance_type.constant_attributes = typ.kernel_constant_attributes
+                    if hasattr(typ, 'kernel_invariants'):
+                        assert isinstance(typ.kernel_invariants, set)
+                        instance_type.constant_attributes = typ.kernel_invariants
 
                     constructor_type = types.TConstructor(instance_type)
                 constructor_type.attributes['__objectid__'] = builtins.TInt32()

artiq/coredevice/core.py

@@ -59,7 +59,7 @@ class Core:
     :param comm_device: name of the device used for communications.
     """
 
-    kernel_constant_attributes = {
+    kernel_invariants = {
         "core", "ref_period", "coarse_ref_period", "ref_multiplier",
         "external_clock",
     }

artiq/coredevice/dds.py

@@ -29,7 +29,7 @@ def dds_batch_exit() -> TNone:
 
 
 class _BatchContextManager:
-    kernel_constant_attributes = {"core", "core_dds"}
+    kernel_invariants = {"core", "core_dds"}
 
     def __init__(self, core_dds):
         self.core_dds = core_dds
@@ -53,7 +53,7 @@ class CoreDDS:
         phase-locked multiple of the RTIO clock.
     """
 
-    kernel_constant_attributes = {"core", "sysclk", "batch"}
+    kernel_invariants = {"core", "sysclk", "batch"}
 
     def __init__(self, dmgr, sysclk, core_device="core"):
         self.core = dmgr.get(core_device)
@@ -88,7 +88,7 @@ class _DDSGeneric:
     :param channel: channel number of the DDS device to control.
     """
 
-    kernel_constant_attributes = {
+    kernel_invariants = {
         "core", "core_dds", "bus_channel", "channel", "pow_width"
     }
 

artiq/coredevice/ttl.py

@@ -10,7 +10,7 @@ class TTLOut:
 
     :param channel: channel number
     """
-    kernel_constant_attributes = {"core", "channel"}
+    kernel_invariants = {"core", "channel"}
 
     def __init__(self, dmgr, channel, core_device="core"):
         self.core = dmgr.get(core_device)
@@ -84,7 +84,7 @@ class TTLInOut:
 
     :param channel: channel number
     """
-    kernel_constant_attributes = {"core", "channel"}
+    kernel_invariants = {"core", "channel"}
 
     def __init__(self, dmgr, channel, core_device="core"):
         self.core = dmgr.get(core_device)
@@ -236,7 +236,7 @@ class TTLClockGen:
 
     :param channel: channel number
     """
-    kernel_constant_attributes = {"core", "channel", "acc_width"}
+    kernel_invariants = {"core", "channel", "acc_width"}
 
     def __init__(self, dmgr, channel, core_device="core"):
         self.core = dmgr.get(core_device)

artiq/test/coredevice/test_rtio.py

@@ -83,7 +83,7 @@ class ClockGeneratorLoopback(EnvExperiment):
 
 
 class PulseRate(EnvExperiment):
-    kernel_constant_attributes = {"core", "ttl_out"}
+    kernel_invariants = {"core", "ttl_out"}
 
     def build(self):
         self.setattr_device("core")
@@ -107,7 +107,7 @@ class PulseRate(EnvExperiment):
 
 
 class PulseRateDDS(EnvExperiment):
-    kernel_constant_attributes = {"core", "core_dds", "dds0", "dds1"}
+    kernel_invariants = {"core", "core_dds", "dds0", "dds1"}
 
     def build(self):
         self.setattr_device("core")

artiq/test/lit/embedding/error_attr_constant.py

@@ -5,7 +5,7 @@ from artiq.language.core import *
 from artiq.language.types import *
 
 class c:
-    kernel_constant_attributes = {'a'}
+    kernel_invariants = {'a'}
 
     def __init__(self):
         self.a = 1