forked from M-Labs/artiq
drtio: more full stack testing
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929a7650a8
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9bbc6eb0ef
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@ -59,6 +59,21 @@ class TestFullStack(unittest.TestCase):
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dut = DUT(2)
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dut = DUT(2)
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kcsrs = dut.master.rt_controller.kcsrs
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kcsrs = dut.master.rt_controller.kcsrs
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ttl_changes = []
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correct_ttl_changes = [
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(203, 0),
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(208, 0),
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(208, 1),
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(214, 1),
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(414, 0),
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(454, 0),
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(494, 0),
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(534, 0),
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(574, 0),
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(614, 0)
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]
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now = 0
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now = 0
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def delay(dt):
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def delay(dt):
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nonlocal now
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nonlocal now
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@ -92,13 +107,15 @@ class TestFullStack(unittest.TestCase):
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wlen += 1
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wlen += 1
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return wlen
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return wlen
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def test():
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def test_init():
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yield from get_fifo_space(0)
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yield from get_fifo_space(0)
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yield from get_fifo_space(1)
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yield from get_fifo_space(1)
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def test_underflow():
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with self.assertRaises(RTIOUnderflow):
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with self.assertRaises(RTIOUnderflow):
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yield from write(0, 0)
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yield from write(0, 0)
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def test_pulses():
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delay(200*8)
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delay(200*8)
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yield from write(0, 1)
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yield from write(0, 1)
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delay(5*8)
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delay(5*8)
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@ -107,11 +124,13 @@ class TestFullStack(unittest.TestCase):
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delay(6*8)
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delay(6*8)
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yield from write(1, 0)
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yield from write(1, 0)
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def test_sequence_error():
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delay(-200*8)
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delay(-200*8)
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with self.assertRaises(RTIOSequenceError):
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with self.assertRaises(RTIOSequenceError):
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yield from write(0, 1)
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yield from write(0, 1)
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delay(200*8)
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delay(200*8)
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def test_fifo_space():
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delay(200*8)
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delay(200*8)
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max_wlen = 0
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max_wlen = 0
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for _ in range(3):
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for _ in range(3):
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@ -124,17 +143,44 @@ class TestFullStack(unittest.TestCase):
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# check that some writes caused FIFO space requests
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# check that some writes caused FIFO space requests
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self.assertGreater(max_wlen, 5)
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self.assertGreater(max_wlen, 5)
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def test_fifo_emptied():
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# wait for all TTL events to execute
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# wait for all TTL events to execute
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for _ in range(40):
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while len(ttl_changes) < len(correct_ttl_changes):
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yield
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yield
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# check "last timestamp passed" FIFO empty condition
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# check "last timestamp passed" FIFO empty condition
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delay(1000*8)
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delay(1000*8)
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wlen = yield from write(0, 1)
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wlen = yield from write(0, 1)
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self.assertEqual(wlen, 2)
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self.assertEqual(wlen, 2)
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def test_tsc_error():
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err_present = yield from kcsrs.err_present.read()
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self.assertEqual(err_present, 0)
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yield from kcsrs.tsc_correction.write(10000000)
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yield from kcsrs.set_time.write(1)
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for i in range(5):
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yield
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delay(10000)
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yield from write(0, 1)
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for i in range(10):
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yield
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err_present = yield from kcsrs.err_present.read()
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err_code = yield from kcsrs.err_code.read()
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self.assertEqual(err_present, 1)
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self.assertEqual(err_code, 2)
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yield from kcsrs.err_present.write(1)
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yield
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err_present = yield from kcsrs.err_present.read()
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self.assertEqual(err_present, 0)
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def test():
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yield from test_init()
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yield from test_underflow()
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yield from test_pulses()
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yield from test_sequence_error()
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yield from test_fifo_space()
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yield from test_fifo_emptied()
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yield from test_tsc_error()
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ttl_changes = []
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@passive
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@passive
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def check_ttls():
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def check_ttls():
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cycle = 0
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cycle = 0
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@ -150,17 +196,5 @@ class TestFullStack(unittest.TestCase):
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run_simulation(dut,
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run_simulation(dut,
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{"sys": test(), "rtio": check_ttls()},
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{"sys": test(), "rtio": check_ttls()},
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{"sys": 8, "rtio": 5, "rtio_rx": 5, "rio": 5, "rio_phy": 5})
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{"sys": 8, "rtio": 5, "rtio_rx": 5, "rio": 5, "rio_phy": 5}, vcd_name="foo.vcd")
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self.assertEqual(ttl_changes, [
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self.assertEqual(ttl_changes, correct_ttl_changes)
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(203, 0),
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(208, 0),
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(208, 1),
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(214, 1),
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(414, 0),
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(454, 0),
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(494, 0),
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(534, 0),
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(574, 0),
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(614, 0)
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])
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