From 9af12230c8f569f4171be32034e64de4522614d1 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 3 Mar 2016 13:19:17 +0800
Subject: [PATCH] soc: add timer to kernel CPU system

---
 artiq/gateware/soc.py                 | 11 +++++++++++
 artiq/gateware/targets/kc705.py       |  7 ++++---
 artiq/gateware/targets/pipistrello.py |  6 ++++--
 3 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/artiq/gateware/soc.py b/artiq/gateware/soc.py
index 4487101aa..e97faa0e5 100644
--- a/artiq/gateware/soc.py
+++ b/artiq/gateware/soc.py
@@ -1,5 +1,6 @@
 from misoc.integration.soc_core import mem_decoder
 from misoc.cores import timer
+from misoc.interconnect import wishbone
 
 from artiq.gateware import amp
 
@@ -29,3 +30,13 @@ class AMPSoC:
                                      self.mailbox.i2)
         self.add_memory_region("mailbox",
                                self.mem_map["mailbox"] | 0x80000000, 4)
+
+        self.submodules.timer_kernel = timer.Timer()
+        timer_csrs = self.timer_kernel.get_csrs()
+        timerwb = wishbone.CSRBank(timer_csrs)
+        self.submodules += timerwb
+        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["timer_kernel"]),
+                                     timerwb.bus)
+        self.add_csr_region("timer_kernel",
+                            self.mem_map["timer_kernel"] | 0x80000000, 32,
+                            timer_csrs)
diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
index 497842058..5854bee17 100755
--- a/artiq/gateware/targets/kc705.py
+++ b/artiq/gateware/targets/kc705.py
@@ -83,7 +83,6 @@ class _RTIOCRG(Module, AutoCSR):
 
 _ams101_dac = [
     ("ams101_dac", 0,
-
         Subsignal("ldac", Pins("XADC:GPIO0")),
         Subsignal("clk", Pins("XADC:GPIO1")),
         Subsignal("mosi", Pins("XADC:GPIO2")),
@@ -95,6 +94,7 @@ _ams101_dac = [
 
 class _NIST_Ions(MiniSoC, AMPSoC):
     csr_map = {
+        "timer_kernel": None,  # mapped on Wishbone instead
         "rtio": None,  # mapped on Wishbone instead
         "rtio_crg": 13,
         "kernel_cpu": 14,
@@ -103,8 +103,9 @@ class _NIST_Ions(MiniSoC, AMPSoC):
     }
     csr_map.update(MiniSoC.csr_map)
     mem_map = {
-        "rtio":     0x20000000, # (shadow @0xa0000000)
-        "mailbox":  0x70000000  # (shadow @0xf0000000)
+        "timer_kernel":  0x10000000, # (shadow @0x90000000)
+        "rtio":          0x20000000, # (shadow @0xa0000000)
+        "mailbox":       0x70000000  # (shadow @0xf0000000)
     }
     mem_map.update(MiniSoC.mem_map)
 
diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py
index ceb39d83f..655ec22b7 100755
--- a/artiq/gateware/targets/pipistrello.py
+++ b/artiq/gateware/targets/pipistrello.py
@@ -103,6 +103,7 @@ TIMESPEC "TSfix_ise4" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
 
 class NIST_QC1(BaseSoC, AMPSoC):
     csr_map = {
+        "timer_kernel": None,  # mapped on Wishbone instead
         "rtio": None,  # mapped on Wishbone instead
         "rtio_crg": 10,
         "kernel_cpu": 11,
@@ -111,8 +112,9 @@ class NIST_QC1(BaseSoC, AMPSoC):
     }
     csr_map.update(BaseSoC.csr_map)
     mem_map = {
-        "rtio":     0x20000000,  # (shadow @0xa0000000)
-        "mailbox":  0x70000000   # (shadow @0xf0000000)
+        "timer_kernel":  0x10000000, # (shadow @0x90000000)
+        "rtio":          0x20000000, # (shadow @0xa0000000)
+        "mailbox":       0x70000000  # (shadow @0xf0000000)
     }
     mem_map.update(BaseSoC.mem_map)