From 9ae57fd51e4bd2434b6ce06352c875812eeda37f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 29 Jan 2019 15:00:49 +0800 Subject: [PATCH] sayma: pass rtio_clk_freq to DDMTD core --- artiq/gateware/targets/sayma_amc.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 4f8bc554f..734ffa015 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -282,7 +282,8 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon): self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) self.csr_devices.append("routing_table") - self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(platform.request("adc_sysref")) + self.submodules.sysref_ddmtd = jesd204_tools.DDMTD( + platform.request("adc_sysref"), rtio_clk_freq) self.csr_devices.append("sysref_ddmtd") platform.add_false_path_constraints(self.ad9154_crg.cd_jesd.clk, self.sysref_ddmtd.cd_helper.clk) @@ -577,7 +578,8 @@ class Satellite(BaseSoC, RTMCommon): self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None - self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(platform.request("adc_sysref")) + self.submodules.sysref_ddmtd = jesd204_tools.DDMTD( + platform.request("adc_sysref"), rtio_clk_freq) self.csr_devices.append("sysref_ddmtd") platform.add_false_path_constraints(self.ad9154_crg.cd_jesd.clk, self.sysref_ddmtd.cd_helper.clk)