forked from M-Labs/artiq
rtio: add spartan6 serdes, 4x and 8x
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from migen.fhdl.std import *
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from artiq.gateware.rtio.phy import ttl_serdes_generic
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class _OSERDES2_8X(Module):
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def __init__(self, pad, stb):
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self.o = Signal(8)
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self.t_in = Signal()
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self.t_out = Signal()
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# # #
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cascade = Signal(4)
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o = self.o
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common = dict(p_DATA_RATE_OQ="SDR", p_DATA_RATE_OT="SDR",
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p_DATA_WIDTH=8, p_OUTPUT_MODE="SINGLE_ENDED", i_TRAIN=0,
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i_CLK0=ClockSignal("rtiox8"), i_CLK1=0,
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i_CLKDIV=ClockSignal("rio_phy"),
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i_IOCE=stb, i_OCE=1, i_TCE=1, i_RST=0,
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i_T4=self.t_in, i_T3=self.t_in,
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i_T2=self.t_in, i_T1=self.t_in)
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self.specials += [
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Instance("OSERDES2", p_SERDES_MODE="MASTER",
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i_D4=o[7], i_D3=o[6], i_D2=o[5], i_D1=o[4],
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i_SHIFTIN1=1, i_SHIFTIN2=1,
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i_SHIFTIN3=cascade[2], i_SHIFTIN4=cascade[3],
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o_SHIFTOUT1=cascade[0], o_SHIFTOUT2=cascade[1],
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o_OQ=pad, o_TQ=self.t_out, **common),
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Instance("OSERDES2", p_SERDES_MODE="SLAVE",
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i_D4=o[3], i_D3=o[2], i_D2=o[1], i_D1=o[0],
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i_SHIFTIN1=cascade[0], i_SHIFTIN2=cascade[1],
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i_SHIFTIN3=1, i_SHIFTIN4=1,
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o_SHIFTOUT3=cascade[2], o_SHIFTOUT4=cascade[3],
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**common),
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]
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class _IOSERDES2_8X(Module):
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def __init__(self, pad, stb):
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self.o = Signal(8)
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self.i = Signal(8)
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self.oe = Signal()
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# # #
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pad_i = Signal()
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pad_o = Signal()
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cascade = Signal()
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i = self.i
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common = dict(p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR",
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p_DATA_WIDTH=8, p_INTERFACE_TYPE="RETIMED",
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i_BITSLIP=0, i_CE0=1, i_IOCE=stb,
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i_RST=0, i_CLK0=ClockSignal("rtiox8"), i_CLK1=0,
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i_CLKDIV=ClockSignal("rio_phy"))
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self.specials += [
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Instance("ISERDES2", p_SERDES_MODE="MASTER",
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o_Q4=i[7], o_Q3=i[6], o_Q2=i[5], o_Q1=i[4],
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o_SHIFTOUT=cascade, i_D=pad_i, i_SHIFTIN=0,
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**common),
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Instance("ISERDES2", p_SERDES_MODE="SLAVE",
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o_Q4=i[3], o_Q3=i[2], o_Q2=i[1], o_Q1=i[0],
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i_D=0, i_SHIFTIN=cascade, **common),
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]
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oserdes = _OSERDES2_8X(pad_o, stb)
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self.submodules += oserdes
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self.specials += Instance("IOBUF",
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i_I=pad_o, o_O=pad_i, i_T=oserdes.t_out,
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io_IO=pad)
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self.comb += [
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oserdes.t_in.eq(~self.oe),
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oserdes.o.eq(self.o),
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]
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class Output_8X(ttl_serdes_generic.Output):
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def __init__(self, pad, stb):
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serdes = _OSERDES2_8X(pad, stb)
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self.submodules += serdes
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ttl_serdes_generic.Output.__init__(self, serdes)
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class Inout_8X(ttl_serdes_generic.Inout):
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def __init__(self, pad, stb):
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serdes = _IOSERDES2_8X(pad, stb)
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self.submodules += serdes
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ttl_serdes_generic.Inout.__init__(self, serdes)
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class _OSERDES2_4X(Module):
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def __init__(self, pad, stb):
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self.o = Signal(4)
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self.t_in = Signal()
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self.t_out = Signal()
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# # #
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o = self.o
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self.specials += Instance("OSERDES2", p_SERDES_MODE="NONE",
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p_DATA_RATE_OQ="SDR", p_DATA_RATE_OT="SDR",
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p_DATA_WIDTH=4, p_OUTPUT_MODE="SINGLE_ENDED",
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i_TRAIN=0, i_CLK0=ClockSignal("rtiox4"),
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i_CLK1=0, i_CLKDIV=ClockSignal("rio_phy"),
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i_IOCE=stb, i_OCE=1, i_TCE=1,
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i_RST=ResetSignal(),
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i_T4=self.t_in, i_T3=self.t_in,
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i_T2=self.t_in, i_T1=self.t_in,
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i_D4=o[3], i_D3=o[2], i_D2=o[1], i_D1=o[0],
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o_OQ=pad, o_TQ=self.t_out)
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class _IOSERDES2_4X(Module):
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def __init__(self, pad, stb):
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self.o = Signal(4)
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self.i = Signal(4)
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self.oe = Signal()
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# # #
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pad_i = Signal()
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pad_o = Signal()
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i = self.i
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self.specials += Instance("ISERDES2", p_SERDES_MODE="NONE",
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p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR",
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p_DATA_WIDTH=4, p_INTERFACE_TYPE="RETIMED",
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i_BITSLIP=0, i_CE0=1, i_IOCE=stb,
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i_RST=0, i_CLK0=ClockSignal("rtiox4"),
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i_CLK1=0, i_CLKDIV=ClockSignal("rio_phy"),
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o_Q4=i[3], o_Q3=i[2], o_Q2=i[1], o_Q1=i[0],
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i_D=pad_i, i_SHIFTIN=0)
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oserdes = _OSERDES2_4X(pad_o, stb)
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self.submodules += oserdes
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self.specials += Instance("IOBUF",
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i_I=pad_o, o_O=pad_i, i_T=oserdes.t_out,
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io_IO=pad)
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self.comb += [
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oserdes.t_in.eq(~self.oe),
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oserdes.o.eq(self.o),
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]
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class Output_4X(ttl_serdes_generic.Output):
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def __init__(self, pad, stb):
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serdes = _OSERDES2_4X(pad, stb)
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self.submodules += serdes
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ttl_serdes_generic.Output.__init__(self, serdes)
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class Inout_4X(ttl_serdes_generic.Inout):
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def __init__(self, pad, stb):
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serdes = _IOSERDES2_4X(pad, stb)
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self.submodules += serdes
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ttl_serdes_generic.Inout.__init__(self, serdes)
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