forked from M-Labs/artiq
firmware: make libbsp a crate
This commit is contained in:
parent
c99388f80f
commit
9a564e07c0
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@ -0,0 +1,8 @@
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[package]
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authors = ["M-Labs"]
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name = "bsp"
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version = "0.0.0"
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[lib]
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name = "bsp"
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path = "lib.rs"
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@ -0,0 +1,4 @@
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#![feature(asm)]
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#![no_std]
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pub mod board;
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@ -2,6 +2,7 @@
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name = "ksupport"
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version = "0.0.0"
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dependencies = [
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"bsp 0.0.0",
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"byteorder 0.5.3 (registry+https://github.com/rust-lang/crates.io-index)",
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"std_artiq 0.0.0",
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]
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@ -10,6 +11,10 @@ dependencies = [
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name = "alloc_artiq"
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version = "0.0.0"
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[[package]]
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name = "bsp"
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version = "0.0.0"
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[[package]]
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name = "byteorder"
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version = "0.5.3"
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@ -10,6 +10,7 @@ crate-type = ["staticlib"]
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[dependencies]
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std_artiq = { path = "../libstd_artiq" }
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bsp = { path = "../libbsp" }
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byteorder = { version = "0.5", default-features = false }
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[profile.dev]
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@ -1,4 +1,4 @@
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use board::csr;
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use bsp::board::csr;
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fn half_period() {
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unsafe {
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@ -16,7 +16,7 @@ fn half_period() {
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#[cfg(has_i2c)]
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mod imp {
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use board::csr;
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use bsp::board::csr;
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fn sda_bit(busno: u32) -> u32 { 1 << (2 * busno + 1) }
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fn scl_bit(busno: u32) -> u32 { 1 << (2 * busno) }
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@ -7,9 +7,8 @@
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extern crate std_artiq as std;
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extern crate libc;
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extern crate byteorder;
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extern crate bsp;
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#[path = "../libbsp/board.rs"]
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mod board;
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#[path = "../runtime/mailbox.rs"]
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mod mailbox;
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@ -1,7 +1,7 @@
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#[path = "../runtime/kernel_proto.rs"]
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mod kernel_proto;
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use board::csr;
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use bsp::board::csr;
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use core::ptr::{read_volatile, write_volatile};
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use ::ArtiqList;
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use ::send;
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@ -2,6 +2,7 @@
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name = "runtime"
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version = "0.0.0"
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dependencies = [
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"bsp 0.0.0",
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"byteorder 0.5.3 (registry+https://github.com/rust-lang/crates.io-index)",
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"fringe 1.1.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"log 0.3.6 (registry+https://github.com/rust-lang/crates.io-index)",
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@ -15,6 +16,10 @@ dependencies = [
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name = "alloc_artiq"
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version = "0.0.0"
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[[package]]
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name = "bsp"
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version = "0.0.0"
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[[package]]
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name = "byteorder"
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version = "0.5.3"
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@ -15,6 +15,7 @@ path = "lib.rs"
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[dependencies]
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std_artiq = { path = "../libstd_artiq", features = ["alloc"] }
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lwip = { path = "../liblwip", default-features = false }
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bsp = { path = "../libbsp" }
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fringe = { version = "= 1.1.0", default-features = false, features = ["alloc"] }
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log = { version = "0.3", default-features = false, features = ["max_level_debug"] }
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log_buffer = { version = "1.0" }
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@ -1,5 +1,5 @@
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use std::io::{self, Write};
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use board::{self, csr};
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use bsp::board::{self, csr};
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use sched::{Waiter, Spawner};
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use sched::{TcpListener, TcpStream, SocketAddr, IP_ANY};
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use analyzer_proto::*;
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@ -1,7 +1,7 @@
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use board::csr;
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use bsp::board::csr;
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const INIT: u64 = ::core::i64::MAX as u64;
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const FREQ: u64 = ::board::csr::CONFIG_CLOCK_FREQUENCY as u64;
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const FREQ: u64 = csr::CONFIG_CLOCK_FREQUENCY as u64;
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pub fn init() {
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unsafe {
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@ -1,5 +1,5 @@
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use core::ptr;
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use board::csr;
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use bsp::board::csr;
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use mailbox;
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use rpc_queue;
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@ -11,6 +11,7 @@ extern crate log_buffer;
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extern crate byteorder;
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extern crate fringe;
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extern crate lwip;
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extern crate bsp;
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use core::fmt::Write;
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use logger::BufferLogger;
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@ -55,8 +56,6 @@ extern fn panic_fmt(args: self::core::fmt::Arguments, file: &'static str, line:
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}
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}
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#[path = "../libbsp/board.rs"]
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mod board;
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mod config;
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mod clock;
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mod rtio_mgt;
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@ -105,7 +104,7 @@ pub unsafe extern fn rust_main() {
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clock::init();
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info!("booting ARTIQ");
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info!("software version {}", GIT_COMMIT);
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info!("gateware version {}", ::board::ident(&mut [0; 64]));
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info!("gateware version {}", bsp::board::ident(&mut [0; 64]));
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let t = clock::get_ms();
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info!("press 'e' to erase startup and idle kernels...");
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@ -138,7 +137,7 @@ pub unsafe extern fn rust_main() {
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#[no_mangle]
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pub unsafe extern fn isr() {
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use board::{irq, csr};
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use bsp::board::{irq, csr};
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extern { fn uart_isr(); }
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let irqs = irq::pending() & irq::get_mask();
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@ -1,5 +1,5 @@
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use core::ptr::{read_volatile, write_volatile};
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use board;
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use bsp::board;
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const MAILBOX: *mut usize = board::mem::MAILBOX_BASE as *mut usize;
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static mut last: usize = 0;
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use std::vec::Vec;
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use std::io;
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use board::csr;
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use bsp::board::csr;
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use sched::{Waiter, Spawner};
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use sched::{UdpSocket, SocketAddr, IP_ANY};
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use moninj_proto::*;
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@ -2,7 +2,7 @@
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use core::ptr::{read_volatile, write_volatile};
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use core::slice;
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use board;
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use bsp::board;
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const SEND_MAILBOX: *mut usize = (board::mem::MAILBOX_BASE + 4) as *mut usize;
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const RECV_MAILBOX: *mut usize = (board::mem::MAILBOX_BASE + 8) as *mut usize;
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@ -1,11 +1,11 @@
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use config;
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use board::csr;
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use bsp::board::csr;
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use sched::Scheduler;
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#[cfg(has_rtio_crg)]
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pub mod crg {
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use clock;
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use board::csr;
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use bsp::board::csr;
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pub fn init() {
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unsafe { csr::rtio_crg::pll_reset_write(0) }
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#[cfg(has_drtio)]
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mod drtio {
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use board::csr;
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use bsp::board::csr;
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use sched::{Scheduler, Waiter, Spawner};
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pub fn startup(scheduler: &Scheduler) {
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@ -10,6 +10,7 @@ use urc::Urc;
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use sched::{ThreadHandle, Waiter, Spawner};
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use sched::{TcpListener, TcpStream, SocketAddr, IP_ANY};
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use byteorder::{ByteOrder, NetworkEndian};
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use bsp::board;
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use rpc_proto as rpc;
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use session_proto as host;
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session: &mut Session) -> io::Result<()> {
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match try!(host_read(stream)) {
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host::Request::Ident =>
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host_write(stream, host::Reply::Ident(::board::ident(&mut [0; 64]))),
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host_write(stream, host::Reply::Ident(board::ident(&mut [0; 64]))),
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// artiq_corelog
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host::Request::Log => {
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