forked from M-Labs/artiq
rtio: add pileup count reporting
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346cca9e90
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9a14081031
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@ -180,6 +180,15 @@ class RTIOIn(_RTIOBase):
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delay(duration)
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self._set_value(0)
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@kernel
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def pileup_count(self):
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"""Returns the number of pileup events (a system clock cycle with too
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many input transitions) since the last call to this function for this
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channel (or since the last RTIO reset).
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"""
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return syscall("rtio_pileup_count", self.channel)
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@kernel
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def count(self):
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"""Poll the RTIO input during all the previously programmed gate
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@ -18,6 +18,7 @@ _syscalls = {
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"rtio_replace": "Iii:n",
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"rtio_sync": "i:n",
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"rtio_get": "i:I",
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"rtio_pileup_count": "i:i",
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"dds_program": "iiI:n",
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}
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@ -71,7 +71,8 @@ class _RTIOBankI(Module):
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self.readable = Signal()
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self.re = Signal()
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self.overflow = Signal()
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self.pileup = Signal()
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self.pileup_count = Signal(16)
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self.pileup_reset = Signal()
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# # #
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@ -79,7 +80,7 @@ class _RTIOBankI(Module):
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values = []
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readables = []
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overflows = []
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pileups = []
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pileup_counts = []
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for n, chif in enumerate(rbus):
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if hasattr(chif, "oe"):
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sensitivity = Signal(2)
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@ -115,22 +116,29 @@ class _RTIOBankI(Module):
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self.sync += If(fifo.we & ~fifo.writable, overflow.eq(1))
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overflows.append(overflow)
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pileup = Signal()
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self.sync += If(chif.i_pileup, pileup.eq(1))
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pileups.append(pileup)
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pileup_count = Signal(16)
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self.sync += \
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If(self.pileup_reset & (self.sel == n),
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pileup_count.eq(0)
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).Elif(chif.i_pileup,
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If(pileup_count != 2**16 - 1, # saturate
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pileup_count.eq(pileup_count + 1)
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)
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)
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pileup_counts.append(pileup_count)
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else:
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timestamps.append(0)
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values.append(0)
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readables.append(0)
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overflows.append(0)
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pileups.append(0)
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pileup_counts.append(0)
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self.comb += [
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self.timestamp.eq(Array(timestamps)[self.sel]),
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self.value.eq(Array(values)[self.sel]),
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self.readable.eq(Array(readables)[self.sel]),
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self.overflow.eq(Array(overflows)[self.sel]),
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self.pileup.eq(Array(pileups)[self.sel])
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self.pileup_count.eq(Array(pileup_counts)[self.sel])
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]
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@ -171,14 +179,16 @@ class RTIO(Module, AutoCSR):
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self._r_o_writable = CSRStatus()
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self._r_o_we = CSR()
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self._r_o_replace = CSR()
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self._r_o_error = CSRStatus()
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self._r_o_underflow = CSRStatus()
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self._r_o_level = CSRStatus(bits_for(ofifo_depth))
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self._r_i_timestamp = CSRStatus(counter_width+fine_ts_width)
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self._r_i_value = CSRStatus()
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self._r_i_readable = CSRStatus()
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self._r_i_re = CSR()
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self._r_i_error = CSRStatus(2)
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self._r_i_overflow = CSRStatus()
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self._r_i_pileup_count = CSRStatus(16)
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self._r_i_pileup_reset = CSR()
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self._r_counter = CSRStatus(counter_width+fine_ts_width)
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self._r_counter_update = CSR()
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@ -209,7 +219,7 @@ class RTIO(Module, AutoCSR):
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self._r_o_writable.status.eq(self.bank_o.writable),
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self.bank_o.we.eq(self._r_o_we.re),
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self.bank_o.replace.eq(self._r_o_replace.re),
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self._r_o_error.status.eq(self.bank_o.underflow),
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self._r_o_underflow.status.eq(self.bank_o.underflow),
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self._r_o_level.status.eq(self.bank_o.level)
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]
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@ -221,8 +231,9 @@ class RTIO(Module, AutoCSR):
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self._r_i_value.status.eq(self.bank_i.value),
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self._r_i_readable.status.eq(self.bank_i.readable),
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self.bank_i.re.eq(self._r_i_re.re),
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self._r_i_error.status.eq(
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Cat(self.bank_i.overflow, self.bank_i.pileup))
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self._r_i_overflow.status.eq(self.bank_i.overflow),
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self._r_i_pileup_count.status.eq(self.bank_i.pileup_count),
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self.bank_i.pileup_reset.eq(self._r_i_pileup_reset.re)
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]
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# Counter access
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@ -27,7 +27,7 @@ void rtio_set(long long int timestamp, int channel, int value)
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rtio_o_value_write(value);
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while(!rtio_o_writable_read());
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rtio_o_we_write(1);
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if(rtio_o_error_read()) {
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if(rtio_o_underflow_read()) {
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rtio_reset_logic_write(1);
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rtio_reset_logic_write(0);
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exception_raise(EID_RTIO_UNDERFLOW);
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@ -40,7 +40,7 @@ void rtio_replace(long long int timestamp, int channel, int value)
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rtio_o_timestamp_write(timestamp);
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rtio_o_value_write(value);
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rtio_o_replace_write(1);
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if(rtio_o_error_read()) {
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if(rtio_o_underflow_read()) {
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rtio_reset_logic_write(1);
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rtio_reset_logic_write(0);
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exception_raise(EID_RTIO_UNDERFLOW);
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@ -68,6 +68,16 @@ long long int rtio_get(int channel)
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return -1;
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}
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int rtio_pileup_count(int channel)
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{
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int r;
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rtio_chan_sel_write(channel);
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r = rtio_i_pileup_count_read();
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rtio_i_pileup_reset_write(1);
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return r;
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}
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#define RTIO_FUD_CHANNEL 4
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void rtio_fud_sync(void)
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@ -96,7 +106,7 @@ void rtio_fud(long long int fud_time)
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rtio_o_timestamp_write(fud_end_time);
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rtio_o_value_write(0);
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rtio_o_we_write(1);
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if(rtio_o_error_read()) {
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if(rtio_o_underflow_read()) {
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rtio_reset_logic_write(1);
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rtio_reset_logic_write(0);
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exception_raise(EID_RTIO_UNDERFLOW);
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@ -7,6 +7,7 @@ void rtio_set(long long int timestamp, int channel, int value);
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void rtio_replace(long long int timestamp, int channel, int value);
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void rtio_sync(int channel);
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long long int rtio_get(int channel);
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int rtio_pileup_count(int channel);
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void rtio_fud_sync(void);
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void rtio_fud(long long int fud_time);
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@ -16,6 +16,7 @@ static const struct symbol syscalls[] = {
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{"rtio_replace", rtio_replace},
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{"rtio_sync", rtio_sync},
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{"rtio_get", rtio_get},
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{"rtio_pileup_count", rtio_pileup_count},
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{"dds_program", dds_program},
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{NULL, NULL}
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};
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