forked from M-Labs/artiq
drtio: order resets wrt writes
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ac792ec52b
commit
9a048c2b3a
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@ -57,19 +57,6 @@ class RTController(Module):
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If(self.csrs.set_time.re, rt_packets.set_time_stb.eq(1))
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]
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# reset
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self.sync += [
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If(rt_packets.reset_ack, rt_packets.reset_stb.eq(0)),
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If(self.csrs.reset.re,
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rt_packets.reset_stb.eq(1),
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rt_packets.reset_phy.eq(0)
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),
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If(self.csrs.reset_phy.re,
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rt_packets.reset_stb.eq(1),
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rt_packets.reset_phy.eq(1)
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),
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]
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# remote channel status cache
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fifo_spaces_mem = Memory(16, channel_count)
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fifo_spaces = fifo_spaces_mem.get_port(write_capable=True)
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@ -80,6 +67,8 @@ class RTController(Module):
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# common packet fields
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rt_packets_fifo_request = Signal()
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rt_packets_reset_request = Signal()
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rt_packets_reset_phy_request = Signal()
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self.comb += [
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fifo_spaces.adr.eq(chan_sel),
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last_timestamps.adr.eq(chan_sel),
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@ -89,6 +78,10 @@ class RTController(Module):
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rt_packets.write_data.eq(self.cri.o_data),
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If(rt_packets_fifo_request,
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rt_packets.write_timestamp.eq(0xffff000000000000)
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).Elif(rt_packets_reset_request,
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rt_packets.write_timestamp.eq(0xffff000000000001)
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).Elif(rt_packets_reset_phy_request,
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rt_packets.write_timestamp.eq(0xffff000000000003)
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).Else(
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rt_packets.write_timestamp.eq(self.cri.o_timestamp)
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)
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@ -141,6 +134,12 @@ class RTController(Module):
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),
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If(self.csrs.o_get_fifo_space.re,
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NextState("GET_FIFO_SPACE")
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),
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If(self.csrs.reset.re,
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NextState("RESET")
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),
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If(self.csrs.reset_phy.re,
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NextState("RESET_PHY")
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)
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)
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fsm.act("WRITE",
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@ -187,6 +186,22 @@ class RTController(Module):
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NextState("IDLE")
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)
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)
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fsm.act("RESET",
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status_wait.eq(1),
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rt_packets_reset_request.eq(1),
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rt_packets.write_stb.eq(1),
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If(rt_packets.write_ack,
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NextState("IDLE")
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)
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)
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fsm.act("RESET_PHY",
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status_wait.eq(1),
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rt_packets_reset_phy_request.eq(1),
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rt_packets.write_stb.eq(1),
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If(rt_packets.write_ack,
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NextState("IDLE")
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)
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)
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# channel state access
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self.comb += [
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@ -430,6 +430,8 @@ class RTPacketMaster(Module):
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# all interface signals in sys domain unless otherwise specified
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# write interface, optimized for throughput
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# writes, fifo space requests, and reset requests need to be ordered
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# and all use the same FIFO.
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self.write_stb = Signal()
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self.write_ack = Signal()
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self.write_timestamp = Signal(64)
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@ -438,12 +440,16 @@ class RTPacketMaster(Module):
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self.write_data = Signal(512)
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# fifo space interface
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# write with timestamp[48:] == 0xffff to make a fifo space request
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# (space requests have to be ordered wrt writes)
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# write with timestamp[48:] == 0xffff and timestamp[0] == 0
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# to make a fifo space request
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self.fifo_space_not = Signal()
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self.fifo_space_not_ack = Signal()
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self.fifo_space = Signal(16)
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# reset interface
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# write with timestamp[48:] == 0xffff, timestamp[0] == 1,
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# and timestamp[1] == phy to make a reset request
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# echo interface
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self.echo_stb = Signal()
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self.echo_ack = Signal()
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@ -457,11 +463,6 @@ class RTPacketMaster(Module):
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# a set_time request pending
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self.tsc_value = Signal(64)
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# reset interface
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self.reset_stb = Signal()
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self.reset_ack = Signal()
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self.reset_phy = Signal()
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# errors
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self.error_not = Signal()
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self.error_not_ack = Signal()
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@ -565,13 +566,6 @@ class RTPacketMaster(Module):
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self.set_time_stb, self.set_time_ack, None,
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set_time_stb, set_time_ack, None)
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reset_stb = Signal()
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reset_ack = Signal()
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reset_phy = Signal()
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self.submodules += _CrossDomainRequest("rtio",
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self.reset_stb, self.reset_ack, self.reset_phy,
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reset_stb, reset_ack, reset_phy)
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echo_stb = Signal()
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echo_ack = Signal()
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self.submodules += _CrossDomainRequest("rtio",
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@ -597,7 +591,11 @@ class RTPacketMaster(Module):
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tx_fsm.act("IDLE",
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If(wfb_readable,
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If(write_timestamp[48:] == 0xffff,
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NextState("FIFO_SPACE")
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If(write_timestamp[0] == 0,
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NextState("FIFO_SPACE")
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).Else(
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NextState("RESET")
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)
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).Else(
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NextState("WRITE")
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)
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@ -608,8 +606,6 @@ class RTPacketMaster(Module):
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).Elif(set_time_stb,
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tsc_value_load.eq(1),
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NextState("SET_TIME")
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).Elif(reset_stb,
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NextState("RESET")
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)
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)
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)
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@ -659,9 +655,9 @@ class RTPacketMaster(Module):
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)
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)
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tx_fsm.act("RESET",
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tx_dp.send("reset", phy=reset_phy),
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tx_dp.send("reset", phy=write_timestamp[1]),
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If(tx_dp.packet_last,
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reset_ack.eq(1),
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wfb_re.eq(1),
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NextState("IDLE")
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)
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)
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