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suservo: fix rtio interface width

This commit is contained in:
Robert Jördens 2018-04-23 15:15:52 +00:00
parent d5eea962ec
commit 99dd9c7a2a
1 changed files with 5 additions and 4 deletions
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9
artiq/gateware/rtio/phy/servo.py
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@ -32,17 +32,18 @@ class RTServoMem(Module):
m_state = servo.m_state.get_port(write_capable=True) m_state = servo.m_state.get_port(write_capable=True)
self.specials += m_state, m_coeff self.specials += m_state, m_coeff
assert w.coeff >= w.state assert w.state >= w.coeff
assert len(m_coeff.dat_w) == 2*w.coeff
assert w.coeff >= w.word assert w.coeff >= w.word
self.rtlink = rtlink.Interface( self.rtlink = rtlink.Interface(
rtlink.OInterface( rtlink.OInterface(
w.coeff, w.state,
# coeff, profile, channel, 2 mems, rw # coeff, profile, channel, 2 mems, rw
3 + w.profile + w.channel + 1 + 1, 3 + w.profile + w.channel + 1 + 1,
enable_replace=False), enable_replace=False),
rtlink.IInterface( rtlink.IInterface(
w.coeff, w.state,
timestamped=False) timestamped=False)
) )
@ -52,7 +53,6 @@ class RTServoMem(Module):
state_sel = self.rtlink.o.address[-2] state_sel = self.rtlink.o.address[-2]
high_coeff = self.rtlink.o.address[0] high_coeff = self.rtlink.o.address[0]
self.comb += [ self.comb += [
self.rtlink.o.busy.eq(active),
m_coeff.adr.eq(self.rtlink.o.address[1:]), m_coeff.adr.eq(self.rtlink.o.address[1:]),
m_coeff.dat_w.eq(Cat(self.rtlink.o.data, self.rtlink.o.data)), m_coeff.dat_w.eq(Cat(self.rtlink.o.data, self.rtlink.o.data)),
m_coeff.we[0].eq(self.rtlink.o.stb & ~high_coeff & m_coeff.we[0].eq(self.rtlink.o.stb & ~high_coeff &
@ -77,6 +77,7 @@ class RTServoMem(Module):
) )
] ]
self.comb += [ self.comb += [
self.rtlink.o.busy.eq(read),
self.rtlink.i.stb.eq(read), self.rtlink.i.stb.eq(read),
self.rtlink.i.data.eq(Mux(state_sel, self.rtlink.i.data.eq(Mux(state_sel,
m_state.dat_r >> w.state - w.coeff, m_state.dat_r >> w.state - w.coeff,