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ttl_serdes_ultrascale: fix, add dummy dci argument

This commit is contained in:
Sebastien Bourdeauducq 2021-02-07 22:31:46 +08:00
parent bbe0c9162a
commit 997a48fb31
1 changed files with 5 additions and 5 deletions
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10
artiq/gateware/rtio/phy/ttl_serdes_ultrascale.py
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@ -48,7 +48,7 @@ class _ISERDESE3(Module):
class _IOSERDESE3(Module): class _IOSERDESE3(Module):
def __init__(self, dw, pad, pad_n=None): def __init__(self, dw):
self.o = Signal(dw) self.o = Signal(dw)
self.i = Signal(dw) self.i = Signal(dw)
self.oe = Signal() self.oe = Signal()
@ -69,8 +69,8 @@ class _IOSERDESE3(Module):
class Output(ttl_serdes_generic.Output): class Output(ttl_serdes_generic.Output):
def __init__(self, dw, pad, pad_n=None): def __init__(self, dw, pad, pad_n=None, dci=False):
serdes = _OSERDESE3(dw, pad, pad_n) serdes = _OSERDESE3(dw)
self.submodules += serdes self.submodules += serdes
ttl_serdes_generic.Output.__init__(self, serdes) ttl_serdes_generic.Output.__init__(self, serdes)
@ -84,8 +84,8 @@ class Output(ttl_serdes_generic.Output):
class InOut(ttl_serdes_generic.InOut): class InOut(ttl_serdes_generic.InOut):
def __init__(self, dw, pad, pad_n=None): def __init__(self, dw, pad, pad_n=None, dci=False):
serdes = _IOSERDESE3(dw, pad, pad_n) serdes = _IOSERDESE3(dw)
self.submodules += serdes self.submodules += serdes
ttl_serdes_generic.InOut.__init__(self, serdes) ttl_serdes_generic.InOut.__init__(self, serdes)