From 98a5607634735f19763db4ff31ae252de93d1c94 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 23 Jan 2018 10:39:20 +0800
Subject: [PATCH] gtp_7series: set clock muxes correctly for second QPLL
 channel

---
 artiq/gateware/drtio/transceiver/gtp_7series.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/artiq/gateware/drtio/transceiver/gtp_7series.py b/artiq/gateware/drtio/transceiver/gtp_7series.py
index f0fa8ed80..796fa77b0 100644
--- a/artiq/gateware/drtio/transceiver/gtp_7series.py
+++ b/artiq/gateware/drtio/transceiver/gtp_7series.py
@@ -86,7 +86,7 @@ class GTPSingle(Module):
                 p_TX_XCLK_SEL="TXUSR",
                 o_TXOUTCLK=self.txoutclk,
                 p_TXOUT_DIV=2,
-                i_TXSYSCLKSEL=0b00,
+                i_TXSYSCLKSEL=0b11,
                 i_TXOUTCLKSEL=0b11,
 
                 # TX Startup/Reset
@@ -136,7 +136,7 @@ class GTPSingle(Module):
                 p_TX_CLK25_DIV=5,
                 p_RX_XCLK_SEL="RXUSR",
                 p_RXOUT_DIV=2,
-                i_RXSYSCLKSEL=0b00,
+                i_RXSYSCLKSEL=0b11,
                 i_RXOUTCLKSEL=0b010,
                 o_RXOUTCLK=self.rxoutclk,
                 i_RXUSRCLK=ClockSignal("rtio_rx"),