forked from M-Labs/artiq
drtio: program Si5324 for 150MHz in 3G config
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@ -19,20 +19,32 @@ from artiq import __version__ as artiq_version
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from artiq import __artiq_dir__ as artiq_dir
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# TODO: parameters for sawg_3g
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# TODO: move I2C programming to softcore CPU
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def get_i2c_program(sys_clk_freq):
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# NOTE: the logical parameters DO NOT MAP to physical values written
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# into registers. They have to be mapped; see the datasheet.
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# DSPLLsim reports the logical parameters in the design summary, not
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# the physical register values (but those are present separately).
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N1_HS = 6 # 10
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NC1_LS = 7 # 8
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N2_HS = 6 # 10
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N2_LS = 20111 # 20112
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N31 = 2513 # 2514
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N32 = 4596 # 4597
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# NOTE: the logical parameters DO NOT MAP to physical values written
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# into registers. They have to be mapped; see the datasheet.
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# DSPLLsim reports the logical parameters in the design summary, not
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# the physical register values.
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pll_dividers_62_5 = {
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"N1_HS" : 6, # 10
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"NC1_LS" : 7, # 8
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"N2_HS" : 6, # 10
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"N2_LS" : 20111, # 20112
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"N31" : 2513, # 2514
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"N32" : 4596 # 4597
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}
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pll_dividers_150 = {
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"N1_HS" : 5, # 9
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"NC1_LS" : 3, # 4
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"N2_HS" : 6, # 10
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"N2_LS" : 33731, # 33732
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"N31" : 9369, # 9370
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"N32" : 7138 # 7139
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}
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# TODO: move I2C programming to softcore CPU
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def get_i2c_program(d, sys_clk_freq):
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i2c_sequence = [
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# PCA9548: select channel 7
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[(0x74 << 1), 1 << 7],
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@ -43,20 +55,20 @@ def get_i2c_program(sys_clk_freq):
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[(0x68 << 1), 3, 0b0101 | 0x10], # SQ_ICAL=1
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[(0x68 << 1), 4, 0b10010010], # AUTOSEL_REG=b10
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[(0x68 << 1), 6, 0x07], # SFOUT1_REG=b111
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[(0x68 << 1), 25, (N1_HS << 5 ) & 0xff],
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[(0x68 << 1), 31, (NC1_LS >> 16) & 0xff],
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[(0x68 << 1), 32, (NC1_LS >> 8 ) & 0xff],
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[(0x68 << 1), 33, (NC1_LS) & 0xff],
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[(0x68 << 1), 40, (N2_HS << 5 ) & 0xff |
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(N2_LS >> 16) & 0xff],
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[(0x68 << 1), 41, (N2_LS >> 8 ) & 0xff],
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[(0x68 << 1), 42, (N2_LS) & 0xff],
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[(0x68 << 1), 43, (N31 >> 16) & 0xff],
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[(0x68 << 1), 44, (N31 >> 8) & 0xff],
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[(0x68 << 1), 45, (N31) & 0xff],
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[(0x68 << 1), 46, (N32 >> 16) & 0xff],
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[(0x68 << 1), 47, (N32 >> 8) & 0xff],
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[(0x68 << 1), 48, (N32) & 0xff],
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[(0x68 << 1), 25, (d["N1_HS"] << 5 ) & 0xff],
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[(0x68 << 1), 31, (d["NC1_LS"] >> 16) & 0xff],
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[(0x68 << 1), 32, (d["NC1_LS"] >> 8 ) & 0xff],
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[(0x68 << 1), 33, (d["NC1_LS"]) & 0xff],
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[(0x68 << 1), 40, (d["N2_HS"] << 5 ) & 0xff |
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(d["N2_LS"] >> 16) & 0xff],
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[(0x68 << 1), 41, (d["N2_LS"] >> 8 ) & 0xff],
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[(0x68 << 1), 42, (d["N2_LS"]) & 0xff],
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[(0x68 << 1), 43, (d["N31"] >> 16) & 0xff],
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[(0x68 << 1), 44, (d["N31"] >> 8) & 0xff],
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[(0x68 << 1), 45, (d["N31"]) & 0xff],
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[(0x68 << 1), 46, (d["N32"] >> 16) & 0xff],
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[(0x68 << 1), 47, (d["N32"] >> 8) & 0xff],
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[(0x68 << 1), 48, (d["N32"]) & 0xff],
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[(0x68 << 1), 137, 0x01], # FASTLOCK=1
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[(0x68 << 1), 136, 0x40], # ICAL=1
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]
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@ -146,8 +158,15 @@ class Satellite(BaseSoC):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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if cfg == "simple_gbe":
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pll_dividers = pll_dividers_62_5
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elif cfg == "sawg_3g":
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pll_dividers = pll_dividers_150
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else:
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raise ValueError
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i2c_master = I2CMaster(platform.request("i2c"))
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sequencer = ResetInserter()(Sequencer(get_i2c_program(self.clk_freq)))
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sequencer = ResetInserter()(
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Sequencer(get_i2c_program(pll_dividers, self.clk_freq)))
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si5324_reset_clock = Si5324ResetClock(platform, self.clk_freq)
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self.submodules += i2c_master, sequencer, si5324_reset_clock
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self.comb += [
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