forked from M-Labs/artiq
drtio/iot: FIFO level
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@ -39,6 +39,12 @@ class IOT(Module):
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fifo_out.raw_bits().eq(fifo.dout)
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]
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# FIFO level
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self.sync += \
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If(rt_packets.fifo_level_update &
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(rt_packets.fifo_level_channel == n),
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rt_packets.fifo_level.eq(fifo.level))
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# FIFO write
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self.comb += fifo.we.eq(rt_packets.write_stb)
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self.sync += \
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