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drtio/iot: FIFO level

This commit is contained in:
Sebastien Bourdeauducq 2016-10-19 18:04:03 +08:00
parent 71480c4d15
commit 9790c5d9ed
1 changed files with 6 additions and 0 deletions
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6
artiq/gateware/drtio/iot.py
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@ -39,6 +39,12 @@ class IOT(Module):
fifo_out.raw_bits().eq(fifo.dout) fifo_out.raw_bits().eq(fifo.dout)
] ]
# FIFO level
self.sync += \
If(rt_packets.fifo_level_update &
(rt_packets.fifo_level_channel == n),
rt_packets.fifo_level.eq(fifo.level))
# FIFO write # FIFO write
self.comb += fifo.we.eq(rt_packets.write_stb) self.comb += fifo.we.eq(rt_packets.write_stb)
self.sync += \ self.sync += \