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firmware: migrate analyzer_proto to new libio.

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This commit is contained in:
whitequark 2018-05-14 12:51:44 +00:00
parent 2999756493
commit 976bb5e935
4 changed files with 6 additions and 3 deletions
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1
artiq/firmware/libproto/Cargo.toml
View File

@ -11,5 +11,6 @@ path = "lib.rs"
byteorder = { version = "1.0", default-features = false }
cslice = { version = "0.3" }
log = { version = "0.4", default-features = false, optional = true }
io = { path = "../libio", features = ["byteorder"] }
std_artiq = { path = "../libstd_artiq", features = ["alloc"] }
dyld = { path = "../libdyld" }

6
artiq/firmware/libproto/analyzer_proto.rs
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@ -1,5 +1,5 @@
use std::io::{self, Write};
use WriteExt;
use io::{Write, Result};
use io::proto::{ProtoWrite};
#[derive(Debug)]
pub struct Header {
@ -11,7 +11,7 @@ pub struct Header {
}
impl Header {
pub fn write_to(&self, writer: &mut Write) -> io::Result<()> {
pub fn write_to<T: Write>(&self, writer: &mut T) -> Result<(), T::WriteError> {
writer.write_u32(self.sent_bytes)?;
writer.write_u64(self.total_byte_count)?;
writer.write_u8(self.overflow_occurred as u8)?;

1
artiq/firmware/libproto/lib.rs
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@ -6,6 +6,7 @@ extern crate cslice;
#[macro_use]
extern crate log;
extern crate io;
extern crate dyld;
extern crate std_artiq as std;

1
artiq/firmware/runtime/Cargo.toml
View File

@ -19,6 +19,7 @@ cslice = { version = "0.3" }
log = { version = "0.4", default-features = false }
managed = { version = "0.6", default-features = false, features = ["alloc", "map"] }
unwind_backtrace = { path = "../libunwind_backtrace" }
io = { path = "../libio", features = ["std_artiq"] }
board = { path = "../libboard", features = ["uart_console", "smoltcp"] }
alloc_list = { path = "../liballoc_list" }
std_artiq = { path = "../libstd_artiq", features = ["alloc", "io_error_alloc"] }