forked from M-Labs/artiq
phaser: synchronize multidds to frame
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@ -13,8 +13,6 @@ class DDSChannel(Module):
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to_rio_phy = ClockDomainsRenamer("rio_phy")
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self.submodules.dds = to_rio_phy(MultiDDS(
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n=5, fwidth=32, xwidth=16, z=19, zl=10, use_lut=use_lut))
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# TODO: latency
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self.comb += self.dds.stb.eq(1)
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regs = []
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for i in self.dds.i:
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regs.extend([i.f, Cat(i.a, i.clr, i.p)])
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@ -70,6 +68,8 @@ class Phaser(Module):
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self.sync.rtio += [
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header.type.eq(1), # reserved
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If(self.serializer.stb,
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self.ch0.dds.stb.eq(1), # synchronize
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self.ch1.dds.stb.eq(1), # synchronize
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header.we.eq(0),
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re_dly.eq(re_dly[1:]),
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),
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