srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

phaser: synchronize multidds to frame

This commit is contained in:
Robert Jördens 2020-08-27 14:28:19 +00:00
parent c10ac2c92a
commit 96fc248d7c
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/gateware/rtio/phy/phaser.py
View File

@ -13,8 +13,6 @@ class DDSChannel(Module):
to_rio_phy = ClockDomainsRenamer("rio_phy") to_rio_phy = ClockDomainsRenamer("rio_phy")
self.submodules.dds = to_rio_phy(MultiDDS( self.submodules.dds = to_rio_phy(MultiDDS(
n=5, fwidth=32, xwidth=16, z=19, zl=10, use_lut=use_lut)) n=5, fwidth=32, xwidth=16, z=19, zl=10, use_lut=use_lut))
# TODO: latency
self.comb += self.dds.stb.eq(1)
regs = [] regs = []
for i in self.dds.i: for i in self.dds.i:
regs.extend([i.f, Cat(i.a, i.clr, i.p)]) regs.extend([i.f, Cat(i.a, i.clr, i.p)])
@ -70,6 +68,8 @@ class Phaser(Module):
self.sync.rtio += [ self.sync.rtio += [
header.type.eq(1), # reserved header.type.eq(1), # reserved
If(self.serializer.stb, If(self.serializer.stb,
self.ch0.dds.stb.eq(1), # synchronize
self.ch1.dds.stb.eq(1), # synchronize
header.we.eq(0), header.we.eq(0),
re_dly.eq(re_dly[1:]), re_dly.eq(re_dly[1:]),
), ),