From 96a5df0dc60e706b995c00455282d7ae858ab4d3 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 8 Oct 2020 16:19:44 +0800 Subject: [PATCH] kasli2: add false path constraint for wrpll helper clock --- artiq/gateware/targets/kasli.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index d1eb75252..9ea276c3a 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -614,6 +614,9 @@ class SatelliteBase(BaseSoC): platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.txoutclk, gtp.rxoutclk) + if with_wrpll: + platform.add_false_path_constraints( + self.wrpll.cd_helper.clk, gtp.rxoutclk) for gtp in self.drtio_transceiver.gtps[1:]: platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(