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gateware/serwb: change serdes clock domain to serwb_serdes

This commit is contained in:
Florent Kermarrec 2017-08-30 15:44:44 +02:00
parent 32ca51faee
commit 9650233007
6 changed files with 96 additions and 96 deletions
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4
artiq/gateware/serwb/core.py
View File

@ -13,10 +13,10 @@ class SERWBCore(Module):
packetizer = Packetizer()
self.submodules += depacketizer, packetizer
tx_cdc = stream.AsyncFIFO([("data", 32)], 8)
tx_cdc = ClockDomainsRenamer({"write": "sys", "read": "serdes"})(tx_cdc)
tx_cdc = ClockDomainsRenamer({"write": "sys", "read": "serwb_serdes"})(tx_cdc)
self.submodules += tx_cdc
rx_cdc = stream.AsyncFIFO([("data", 32)], 8)
rx_cdc = ClockDomainsRenamer({"write": "serdes", "read": "sys"})(rx_cdc)
rx_cdc = ClockDomainsRenamer({"write": "serwb_serdes", "read": "sys"})(rx_cdc)
self.submodules += rx_cdc
self.comb += [
# core <--> etherbone

60
artiq/gateware/serwb/kusphy.py
View File

@ -24,9 +24,9 @@ class KUSSerdes(Module):
# # #
self.submodules.encoder = ClockDomainsRenamer("serdes")(
self.submodules.encoder = ClockDomainsRenamer("serwb_serdes")(
Encoder(4, True))
self.decoders = [ClockDomainsRenamer("serdes")(
self.decoders = [ClockDomainsRenamer("serwb_serdes")(
Decoder(True)) for _ in range(4)]
self.submodules += self.decoders
@ -37,16 +37,16 @@ class KUSSerdes(Module):
# - linerate/10 slave refclk generated on clk_pads
# In Slave mode:
# - linerate/10 pll refclk provided by clk_pads
self.clock_domains.cd_serdes = ClockDomain()
self.clock_domains.cd_serdes_5x = ClockDomain()
self.clock_domains.cd_serdes_20x = ClockDomain(reset_less=True)
self.clock_domains.cd_serwb_serdes = ClockDomain()
self.clock_domains.cd_serwb_serdes_5x = ClockDomain()
self.clock_domains.cd_serwb_serdes_20x = ClockDomain(reset_less=True)
self.comb += [
self.cd_serdes.clk.eq(pll.serdes_clk),
self.cd_serdes_5x.clk.eq(pll.serdes_5x_clk),
self.cd_serdes_20x.clk.eq(pll.serdes_20x_clk)
self.cd_serwb_serdes.clk.eq(pll.serwb_serdes_clk),
self.cd_serwb_serdes_5x.clk.eq(pll.serwb_serdes_5x_clk),
self.cd_serwb_serdes_20x.clk.eq(pll.serwb_serdes_20x_clk)
]
self.specials += AsyncResetSynchronizer(self.cd_serdes, ~pll.lock)
self.comb += self.cd_serdes_5x.rst.eq(self.cd_serdes.rst)
self.specials += AsyncResetSynchronizer(self.cd_serwb_serdes, ~pll.lock)
self.comb += self.cd_serwb_serdes_5x.rst.eq(self.cd_serwb_serdes.rst)
# control/status cdc
tx_idle = Signal()
@ -59,20 +59,20 @@ class KUSSerdes(Module):
rx_delay_en_vtc = Signal()
rx_delay_ce = Signal()
self.specials += [
MultiReg(self.tx_idle, tx_idle, "serdes"),
MultiReg(self.tx_comma, tx_comma, "serdes"),
MultiReg(self.tx_idle, tx_idle, "serwb_serdes"),
MultiReg(self.tx_comma, tx_comma, "serwb_serdes"),
MultiReg(rx_idle, self.rx_idle, "sys"),
MultiReg(rx_comma, self.rx_comma, "sys"),
MultiReg(self.rx_bitslip_value, rx_bitslip_value, "serdes"),
MultiReg(self.rx_delay_inc, rx_delay_inc, "serdes_5x"),
MultiReg(self.rx_delay_en_vtc, rx_delay_en_vtc, "serdes_5x")
MultiReg(self.rx_bitslip_value, rx_bitslip_value, "serwb_serdes"),
MultiReg(self.rx_delay_inc, rx_delay_inc, "serwb_serdes_5x"),
MultiReg(self.rx_delay_en_vtc, rx_delay_en_vtc, "serwb_serdes_5x")
]
self.submodules.do_rx_delay_rst = PulseSynchronizer("sys", "serdes_5x")
self.submodules.do_rx_delay_rst = PulseSynchronizer("sys", "serwb_serdes_5x")
self.comb += [
rx_delay_rst.eq(self.do_rx_delay_rst.o),
self.do_rx_delay_rst.i.eq(self.rx_delay_rst)
]
self.submodules.do_rx_delay_ce = PulseSynchronizer("sys", "serdes_5x")
self.submodules.do_rx_delay_ce = PulseSynchronizer("sys", "serwb_serdes_5x")
self.comb += [
rx_delay_ce.eq(self.do_rx_delay_ce.o),
self.do_rx_delay_ce.i.eq(self.rx_delay_ce)
@ -80,7 +80,7 @@ class KUSSerdes(Module):
# tx clock (linerate/10)
if mode == "master":
self.submodules.tx_clk_gearbox = Gearbox(40, "serdes", 8, "serdes_5x")
self.submodules.tx_clk_gearbox = Gearbox(40, "serwb_serdes", 8, "serwb_serdes_5x")
self.comb += self.tx_clk_gearbox.i.eq((0b1111100000 << 30) |
(0b1111100000 << 20) |
(0b1111100000 << 10) |
@ -92,8 +92,8 @@ class KUSSerdes(Module):
p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
o_OQ=clk_o,
i_RST=ResetSignal("serdes"),
i_CLK=ClockSignal("serdes_20x"), i_CLKDIV=ClockSignal("serdes_5x"),
i_RST=ResetSignal("serwb_serdes"),
i_CLK=ClockSignal("serwb_serdes_20x"), i_CLKDIV=ClockSignal("serwb_serdes_5x"),
i_D=self.tx_clk_gearbox.o
),
Instance("OBUFDS",
@ -105,7 +105,7 @@ class KUSSerdes(Module):
# tx datapath
# tx_data -> encoders -> gearbox -> serdes
self.submodules.tx_gearbox = Gearbox(40, "serdes", 8, "serdes_5x")
self.submodules.tx_gearbox = Gearbox(40, "serwb_serdes", 8, "serwb_serdes_5x")
self.comb += [
If(tx_comma,
self.encoder.k[0].eq(1),
@ -117,7 +117,7 @@ class KUSSerdes(Module):
self.encoder.d[3].eq(self.tx_data[24:32])
)
]
self.sync.serdes += \
self.sync.serwb_serdes += \
If(tx_idle,
self.tx_gearbox.i.eq(0)
).Else(
@ -131,8 +131,8 @@ class KUSSerdes(Module):
p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
o_OQ=serdes_o,
i_RST=ResetSignal("serdes"),
i_CLK=ClockSignal("serdes_20x"), i_CLKDIV=ClockSignal("serdes_5x"),
i_RST=ResetSignal("serwb_serdes"),
i_CLK=ClockSignal("serwb_serdes_20x"), i_CLKDIV=ClockSignal("serwb_serdes_5x"),
i_D=self.tx_gearbox.o
),
Instance("OBUFDS",
@ -166,8 +166,8 @@ class KUSSerdes(Module):
# rx datapath
# serdes -> gearbox -> bitslip -> decoders -> rx_data
self.submodules.rx_gearbox = Gearbox(8, "serdes_5x", 40, "serdes")
self.submodules.rx_bitslip = ClockDomainsRenamer("serdes")(BitSlip(40))
self.submodules.rx_gearbox = Gearbox(8, "serwb_serdes_5x", 40, "serwb_serdes")
self.submodules.rx_bitslip = ClockDomainsRenamer("serwb_serdes")(BitSlip(40))
serdes_i_nodelay = Signal()
self.specials += [
@ -187,7 +187,7 @@ class KUSSerdes(Module):
p_DELAY_FORMAT="COUNT", p_DELAY_SRC="IDATAIN",
p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
i_CLK=ClockSignal("serdes_5x"),
i_CLK=ClockSignal("serwb_serdes_5x"),
i_RST=rx_delay_rst, i_LOAD=0,
i_INC=rx_delay_inc, i_EN_VTC=rx_delay_en_vtc,
i_CE=rx_delay_ce,
@ -198,10 +198,10 @@ class KUSSerdes(Module):
p_DATA_WIDTH=8,
i_D=serdes_i_delayed,
i_RST=ResetSignal("serdes"),
i_RST=ResetSignal("serwb_serdes"),
i_FIFO_RD_CLK=0, i_FIFO_RD_EN=0,
i_CLK=ClockSignal("serdes_20x"), i_CLK_B=~ClockSignal("serdes_20x"),
i_CLKDIV=ClockSignal("serdes_5x"),
i_CLK=ClockSignal("serwb_serdes_20x"), i_CLK_B=~ClockSignal("serwb_serdes_20x"),
i_CLKDIV=ClockSignal("serwb_serdes_5x"),
o_Q=serdes_q
)
]

42
artiq/gateware/serwb/phy.py
View File

@ -325,27 +325,27 @@ class SERWBPLL(Module):
self.lock = Signal()
self.refclk = Signal()
self.serdes_clk = Signal()
self.serdes_20x_clk = Signal()
self.serdes_5x_clk = Signal()
self.serwb_serdes_clk = Signal()
self.serwb_serdes_20x_clk = Signal()
self.serwb_serdes_5x_clk = Signal()
# # #
#----------------------
#----------------------------
# refclk: 125MHz
# vco: 1250MHz
#----------------------
# serdes: 31.25MHz
# serdes_20x: 625MHz
# serdes_5x: 156.25MHz
#----------------------
#----------------------------
# serwb_serdes: 31.25MHz
# serwb_serdes_20x: 625MHz
# serwb_serdes_5x: 156.25MHz
#----------------------------
self.linerate = linerate
pll_locked = Signal()
pll_fb = Signal()
pll_serdes_clk = Signal()
pll_serdes_20x_clk = Signal()
pll_serdes_5x_clk = Signal()
pll_serwb_serdes_clk = Signal()
pll_serwb_serdes_20x_clk = Signal()
pll_serwb_serdes_5x_clk = Signal()
self.specials += [
Instance("PLLE2_BASE",
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
@ -356,21 +356,21 @@ class SERWBPLL(Module):
i_CLKIN1=self.refclk, i_CLKFBIN=pll_fb,
o_CLKFBOUT=pll_fb,
# 31.25MHz: serdes
# 31.25MHz: serwb_serdes
p_CLKOUT0_DIVIDE=40//vco_div, p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=pll_serdes_clk,
o_CLKOUT0=pll_serwb_serdes_clk,
# 625MHz: serdes_20x
# 625MHz: serwb_serdes_20x
p_CLKOUT1_DIVIDE=2//vco_div, p_CLKOUT1_PHASE=0.0,
o_CLKOUT1=pll_serdes_20x_clk,
o_CLKOUT1=pll_serwb_serdes_20x_clk,
# 156.25MHz: serdes_5x
# 156.25MHz: serwb_serdes_5x
p_CLKOUT2_DIVIDE=8//vco_div, p_CLKOUT2_PHASE=0.0,
o_CLKOUT2=pll_serdes_5x_clk
o_CLKOUT2=pll_serwb_serdes_5x_clk
),
Instance("BUFG", i_I=pll_serdes_clk, o_O=self.serdes_clk),
Instance("BUFG", i_I=pll_serdes_20x_clk, o_O=self.serdes_20x_clk),
Instance("BUFG", i_I=pll_serdes_5x_clk, o_O=self.serdes_5x_clk)
Instance("BUFG", i_I=pll_serwb_serdes_clk, o_O=self.serwb_serdes_clk),
Instance("BUFG", i_I=pll_serwb_serdes_20x_clk, o_O=self.serwb_serdes_20x_clk),
Instance("BUFG", i_I=pll_serwb_serdes_5x_clk, o_O=self.serwb_serdes_5x_clk)
]
self.specials += MultiReg(pll_locked, self.lock)

50
artiq/gateware/serwb/s7phy.py
View File

@ -23,9 +23,9 @@ class S7Serdes(Module):
# # #
self.submodules.encoder = ClockDomainsRenamer("serdes")(
self.submodules.encoder = ClockDomainsRenamer("serwb_serdes")(
Encoder(4, True))
self.decoders = [ClockDomainsRenamer("serdes")(
self.decoders = [ClockDomainsRenamer("serwb_serdes")(
Decoder(True)) for _ in range(4)]
self.submodules += self.decoders
@ -36,16 +36,16 @@ class S7Serdes(Module):
# - linerate/10 slave refclk generated on clk_pads
# In Slave mode:
# - linerate/10 pll refclk provided by clk_pads
self.clock_domains.cd_serdes = ClockDomain()
self.clock_domains.cd_serdes_5x = ClockDomain()
self.clock_domains.cd_serdes_20x = ClockDomain(reset_less=True)
self.clock_domains.cd_serwb_serdes = ClockDomain()
self.clock_domains.cd_serwb_serdes_5x = ClockDomain()
self.clock_domains.cd_serwb_serdes_20x = ClockDomain(reset_less=True)
self.comb += [
self.cd_serdes.clk.eq(pll.serdes_clk),
self.cd_serdes_5x.clk.eq(pll.serdes_5x_clk),
self.cd_serdes_20x.clk.eq(pll.serdes_20x_clk)
self.cd_serwb_serdes.clk.eq(pll.serwb_serdes_clk),
self.cd_serwb_serdes_5x.clk.eq(pll.serwb_serdes_5x_clk),
self.cd_serwb_serdes_20x.clk.eq(pll.serwb_serdes_20x_clk)
]
self.specials += AsyncResetSynchronizer(self.cd_serdes, ~pll.lock)
self.comb += self.cd_serdes_5x.rst.eq(self.cd_serdes.rst)
self.specials += AsyncResetSynchronizer(self.cd_serwb_serdes, ~pll.lock)
self.comb += self.cd_serwb_serdes_5x.rst.eq(self.cd_serwb_serdes.rst)
# control/status cdc
tx_idle = Signal()
@ -54,16 +54,16 @@ class S7Serdes(Module):
rx_comma = Signal()
rx_bitslip_value = Signal(6)
self.specials += [
MultiReg(self.tx_idle, tx_idle, "serdes"),
MultiReg(self.tx_comma, tx_comma, "serdes"),
MultiReg(self.tx_idle, tx_idle, "serwb_serdes"),
MultiReg(self.tx_comma, tx_comma, "serwb_serdes"),
MultiReg(rx_idle, self.rx_idle, "sys"),
MultiReg(rx_comma, self.rx_comma, "sys")
]
self.specials += MultiReg(self.rx_bitslip_value, rx_bitslip_value, "serdes"),
self.specials += MultiReg(self.rx_bitslip_value, rx_bitslip_value, "serwb_serdes"),
# tx clock (linerate/10)
if mode == "master":
self.submodules.tx_clk_gearbox = Gearbox(40, "serdes", 8, "serdes_5x")
self.submodules.tx_clk_gearbox = Gearbox(40, "serwb_serdes", 8, "serwb_serdes_5x")
self.comb += self.tx_clk_gearbox.i.eq((0b1111100000 << 30) |
(0b1111100000 << 20) |
(0b1111100000 << 10) |
@ -77,8 +77,8 @@ class S7Serdes(Module):
o_OQ=clk_o,
i_OCE=1,
i_RST=ResetSignal("serdes"),
i_CLK=ClockSignal("serdes_20x"), i_CLKDIV=ClockSignal("serdes_5x"),
i_RST=ResetSignal("serwb_serdes"),
i_CLK=ClockSignal("serwb_serdes_20x"), i_CLKDIV=ClockSignal("serwb_serdes_5x"),
i_D1=self.tx_clk_gearbox.o[0], i_D2=self.tx_clk_gearbox.o[1],
i_D3=self.tx_clk_gearbox.o[2], i_D4=self.tx_clk_gearbox.o[3],
i_D5=self.tx_clk_gearbox.o[4], i_D6=self.tx_clk_gearbox.o[5],
@ -93,7 +93,7 @@ class S7Serdes(Module):
# tx datapath
# tx_data -> encoders -> gearbox -> serdes
self.submodules.tx_gearbox = Gearbox(40, "serdes", 8, "serdes_5x")
self.submodules.tx_gearbox = Gearbox(40, "serwb_serdes", 8, "serwb_serdes_5x")
self.comb += [
If(tx_comma,
self.encoder.k[0].eq(1),
@ -105,7 +105,7 @@ class S7Serdes(Module):
self.encoder.d[3].eq(self.tx_data[24:32])
)
]
self.sync.serdes += \
self.sync.serwb_serdes += \
If(tx_idle,
self.tx_gearbox.i.eq(0)
).Else(
@ -121,8 +121,8 @@ class S7Serdes(Module):
o_OQ=serdes_o,
i_OCE=1,
i_RST=ResetSignal("serdes"),
i_CLK=ClockSignal("serdes_20x"), i_CLKDIV=ClockSignal("serdes_5x"),
i_RST=ResetSignal("serwb_serdes"),
i_CLK=ClockSignal("serwb_serdes_20x"), i_CLKDIV=ClockSignal("serwb_serdes_5x"),
i_D1=self.tx_gearbox.o[0], i_D2=self.tx_gearbox.o[1],
i_D3=self.tx_gearbox.o[2], i_D4=self.tx_gearbox.o[3],
i_D5=self.tx_gearbox.o[4], i_D6=self.tx_gearbox.o[5],
@ -159,8 +159,8 @@ class S7Serdes(Module):
# rx datapath
# serdes -> gearbox -> bitslip -> decoders -> rx_data
self.submodules.rx_gearbox = Gearbox(8, "serdes_5x", 40, "serdes")
self.submodules.rx_bitslip = ClockDomainsRenamer("serdes")(BitSlip(40))
self.submodules.rx_gearbox = Gearbox(8, "serwb_serdes_5x", 40, "serwb_serdes")
self.submodules.rx_bitslip = ClockDomainsRenamer("serwb_serdes")(BitSlip(40))
serdes_i_nodelay = Signal()
self.specials += [
@ -194,9 +194,9 @@ class S7Serdes(Module):
i_DDLY=serdes_i_delayed,
i_CE1=1,
i_RST=ResetSignal("serdes"),
i_CLK=ClockSignal("serdes_20x"), i_CLKB=~ClockSignal("serdes_20x"),
i_CLKDIV=ClockSignal("serdes_5x"),
i_RST=ResetSignal("serwb_serdes"),
i_CLK=ClockSignal("serwb_serdes_20x"), i_CLKB=~ClockSignal("serwb_serdes_20x"),
i_CLKDIV=ClockSignal("serwb_serdes_5x"),
i_BITSLIP=0,
o_Q8=serdes_q[0], o_Q7=serdes_q[1],
o_Q6=serdes_q[2], o_Q5=serdes_q[3],

16
artiq/gateware/targets/sayma_amc_standalone.py
View File

@ -69,16 +69,16 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
self.submodules.serwb_phy = serwb_phy
self.csr_devices.append("serwb_phy")
serwb_phy.serdes.cd_serdes.clk.attr.add("keep")
serwb_phy.serdes.cd_serdes_20x.clk.attr.add("keep")
serwb_phy.serdes.cd_serdes_5x.clk.attr.add("keep")
platform.add_period_constraint(serwb_phy.serdes.cd_serdes.clk, 32.0),
platform.add_period_constraint(serwb_phy.serdes.cd_serdes_20x.clk, 1.6),
platform.add_period_constraint(serwb_phy.serdes.cd_serdes_5x.clk, 6.4)
serwb_phy.serdes.cd_serwb_serdes.clk.attr.add("keep")
serwb_phy.serdes.cd_serwb_serdes_20x.clk.attr.add("keep")
serwb_phy.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
platform.add_period_constraint(serwb_phy.serdes.cd_serwb_serdes.clk, 32.0),
platform.add_period_constraint(serwb_phy.serdes.cd_serwb_serdes_20x.clk, 1.6),
platform.add_period_constraint(serwb_phy.serdes.cd_serwb_serdes_5x.clk, 6.4)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
serwb_phy.serdes.cd_serdes.clk,
serwb_phy.serdes.cd_serdes_5x.clk)
serwb_phy.serdes.cd_serwb_serdes.clk,
serwb_phy.serdes.cd_serwb_serdes_5x.clk)
# serwb slave
serwb_core = serwb.core.SERWBCore(serwb_phy, int(self.clk_freq), mode="slave")

16
artiq/gateware/targets/sayma_rtm.py
View File

@ -110,16 +110,16 @@ class SaymaRTM(Module):
self.submodules.serwb_phy = serwb_phy
self.comb += self.crg.reset.eq(serwb_phy.init.reset)
serwb_phy.serdes.cd_serdes.clk.attr.add("keep")
serwb_phy.serdes.cd_serdes_20x.clk.attr.add("keep")
serwb_phy.serdes.cd_serdes_5x.clk.attr.add("keep")
platform.add_period_constraint(serwb_phy.serdes.cd_serdes.clk, 32.0),
platform.add_period_constraint(serwb_phy.serdes.cd_serdes_20x.clk, 1.6),
platform.add_period_constraint(serwb_phy.serdes.cd_serdes_5x.clk, 6.4)
serwb_phy.serdes.cd_serwb_serdes.clk.attr.add("keep")
serwb_phy.serdes.cd_serwb_serdes_20x.clk.attr.add("keep")
serwb_phy.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
platform.add_period_constraint(serwb_phy.serdes.cd_serwb_serdes.clk, 32.0),
platform.add_period_constraint(serwb_phy.serdes.cd_serwb_serdes_20x.clk, 1.6),
platform.add_period_constraint(serwb_phy.serdes.cd_serwb_serdes_5x.clk, 6.4)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
serwb_phy.serdes.cd_serdes.clk,
serwb_phy.serdes.cd_serdes_5x.clk)
serwb_phy.serdes.cd_serwb_serdes.clk,
serwb_phy.serdes.cd_serwb_serdes_5x.clk)
# serwb master
serwb_core = serwb.core.SERWBCore(serwb_phy, int(clk_freq), mode="master")