forked from M-Labs/artiq
Update install instructions to reflect that LLVM is always needed.
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@ -70,35 +70,19 @@ Next step (for KC705) is to flash MAC and IP addresses to the board:
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Installing from source
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Installing from source
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----------------------
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----------------------
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You can skip this if you already installed from conda.
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You can skip the first two steps if you already installed from conda.
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Preparing the core device FPGA board
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Preparing the build environment for the core device
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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These steps are required to generate bitstream (``.bit``) files, build the MiSoC BIOS and ARTIQ runtime, and flash FPGA boards. If the board is already flashed, you may skip those steps and go directly to `Installing the host-side software`.
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These steps are required to generate code that can run on the core
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device. They are necessary both for building the MiSoC BIOS
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* Install the FPGA vendor tools (e.g. Xilinx ISE and/or Vivado):
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and the ARTIQ kernels.
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* Get Xilinx tools from http://www.xilinx.com/support/download/index.htm. ISE can build bitstreams both for boards using the Spartan-6 (Pipistrello) and 7-series devices (KC705), while Vivado supports only boards using 7-series devices.
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* The Pipistrello is supported by Webpack, the KC705 is not.
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* During the Xilinx toolchain installation, uncheck ``Install cable drivers`` (they are not required as we use better and open source alternatives).
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* Create a development directory: ::
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* Create a development directory: ::
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$ mkdir ~/artiq-dev
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$ mkdir ~/artiq-dev
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* Install Migen: ::
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$ cd ~/artiq-dev
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$ git clone https://github.com/m-labs/migen
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$ cd migen
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$ python3 setup.py develop --user
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.. note::
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The options ``develop`` and ``--user`` are for setup.py to install Migen in ``~/.local/lib/python3.4``.
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* Install OpenRISC binutils (or1k-linux-...): ::
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* Install OpenRISC binutils (or1k-linux-...): ::
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$ cd ~/artiq-dev
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$ cd ~/artiq-dev
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@ -133,6 +117,29 @@ These steps are required to generate bitstream (``.bit``) files, build the MiSoC
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.. note::
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.. note::
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Compilation of LLVM can take more than 30 min on some machines.
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Compilation of LLVM can take more than 30 min on some machines.
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Preparing the core device FPGA board
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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These steps are required to generate bitstream (``.bit``) files, build the MiSoC BIOS and ARTIQ runtime, and flash FPGA boards. If the board is already flashed, you may skip those steps and go directly to `Installing the host-side software`.
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* Install the FPGA vendor tools (e.g. Xilinx ISE and/or Vivado):
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* Get Xilinx tools from http://www.xilinx.com/support/download/index.htm. ISE can build bitstreams both for boards using the Spartan-6 (Pipistrello) and 7-series devices (KC705), while Vivado supports only boards using 7-series devices.
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* The Pipistrello is supported by Webpack, the KC705 is not.
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* During the Xilinx toolchain installation, uncheck ``Install cable drivers`` (they are not required as we use better and open source alternatives).
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* Install Migen: ::
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$ cd ~/artiq-dev
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$ git clone https://github.com/m-labs/migen
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$ cd migen
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$ python3 setup.py develop --user
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.. note::
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The options ``develop`` and ``--user`` are for setup.py to install Migen in ``~/.local/lib/python3.4``.
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.. _install-xc3sprog:
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.. _install-xc3sprog:
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* Install JTAG tools needed to program the Pipistrello and KC705:
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* Install JTAG tools needed to program the Pipistrello and KC705:
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@ -297,7 +304,7 @@ Installing the host-side software
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$ patch -p1 < ~/artiq-dev/artiq/misc/llvmlite-add-all-targets.patch
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$ patch -p1 < ~/artiq-dev/artiq/misc/llvmlite-add-all-targets.patch
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$ patch -p1 < ~/artiq-dev/artiq/misc/llvmlite-rename.patch
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$ patch -p1 < ~/artiq-dev/artiq/misc/llvmlite-rename.patch
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$ patch -p1 < ~/artiq-dev/artiq/misc/llvmlite-build-as-debug-on-windows.patch
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$ patch -p1 < ~/artiq-dev/artiq/misc/llvmlite-build-as-debug-on-windows.patch
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$ PATH=/usr/local/llvm-or1k/bin:$PATH sudo -E python3 setup.py install
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$ LLVM_CONFIG=/usr/local/llvm-or1k/bin/llvm-config python3 setup.py install --user
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.. note::
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.. note::
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llvmlite is in development and its API is not stable yet. Commit ID ``11a8303d02e3d6dd2d1e0e9065701795cd8a979f`` is known to work.
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llvmlite is in development and its API is not stable yet. Commit ID ``11a8303d02e3d6dd2d1e0e9065701795cd8a979f`` is known to work.
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