forked from M-Labs/artiq
gateware.spi: style
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@ -282,10 +282,9 @@ class SPIMaster(Module):
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])
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assert len(xfer) <= len(bus.dat_w)
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# SPI
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spi = SPIMachine(data_width, clock_width=len(config.div_read),
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bits_width=len(xfer.read_length))
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self.submodules += spi
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self.submodules.spi = spi = SPIMachine(
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data_width, clock_width=len(config.div_read),
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bits_width=len(xfer.read_length))
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wb_we = Signal()
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pending = Signal()
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@ -344,12 +343,12 @@ class SPIMaster(Module):
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self.comb += [
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clk_t.oe.eq(~config.offline),
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clk_t.o.eq((spi.cg.clk & spi.cs) ^ config.clk_polarity),
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mosi_t.oe.eq(~config.offline & spi.cs &
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(spi.oe | ~config.half_duplex)),
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clk_t.o.eq((spi.cg.clk & spi.cs) ^ config.clk_polarity),
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mosi_t.o.eq(spi.reg.o),
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spi.reg.i.eq(Mux(config.half_duplex, mosi_t.i,
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getattr(pads, "miso", mosi_t.i))),
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mosi_t.o.eq(spi.reg.o),
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]
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@ -438,32 +437,31 @@ def _test_gen(bus):
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hex(wdata), hex(rdata), hex(a), hex(b))
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class _TestPads:
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def __init__(self):
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self.cs_n = Signal(3)
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self.cs_n = Signal(2)
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self.clk = Signal()
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self.mosi = Signal()
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self.miso = Signal()
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class _TestTristate(Module):
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def __init__(self, t):
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oe = Signal()
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self.comb += [
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t.target.eq(t.o),
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oe.eq(t.oe),
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t.i.eq(t.o),
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]
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if __name__ == "__main__":
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from migen.fhdl.specials import Tristate
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class T(Module):
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def __init__(self, t):
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oe = Signal()
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self.comb += [
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t.target.eq(t.o),
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oe.eq(t.oe),
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t.i.eq(t.o),
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]
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Tristate.lower = staticmethod(lambda dr: T(dr))
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pads = _TestPads()
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dut = SPIMaster(pads)
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dut.comb += pads.miso.eq(pads.mosi)
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# from migen.fhdl.verilog import convert
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# print(convert(dut))
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Tristate.lower = _TestTristate
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run_simulation(dut, _test_gen(dut.bus), vcd_name="spi_master.vcd")
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