diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py
index 0a110a0d7..42dc87dac 100755
--- a/artiq/gateware/targets/pipistrello.py
+++ b/artiq/gateware/targets/pipistrello.py
@@ -184,9 +184,9 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
         # the last TTL is used for ClockGen
         for i in range(15):
             if i in (0, 1):
-                phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i),
-                                                    self.rtio_crg.rtiox4_stb)
-            elif i in (2,):  # ttl2 can run on a 8x serdes if xtrig is not used
+                phy = ttl_serdes_spartan6.Inout_4X(platform.request("ttl", i),
+                                                   self.rtio_crg.rtiox4_stb)
+            elif i in (2,):
                 phy = ttl_serdes_spartan6.Output_8X(platform.request("ttl", i),
                                                     self.rtio_crg.rtiox8_stb)
             else:
diff --git a/doc/manual/core_device.rst b/doc/manual/core_device.rst
index 541d97ae6..e70b30f11 100644
--- a/doc/manual/core_device.rst
+++ b/doc/manual/core_device.rst
@@ -146,7 +146,9 @@ The TTL lines are mapped to RTIO channels as follows:
 +--------------+------------+--------------+
 | RTIO channel | TTL line   | Capability   |
 +==============+============+==============+
-| 0-14         | B0-14      | Output       |
+| 0-1          | B0-1       | Input+Output |
++--------------+------------+--------------+
+| 2-14         | B2-14      | Output       |
 +--------------+------------+--------------+
 | 15           | USER_LED_1 | Output       |
 +--------------+------------+--------------+