forked from M-Labs/artiq
parent
8deb269b9a
commit
92fd705990
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@ -14,8 +14,8 @@ struct slice {
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void send_to_core_log(struct slice str);
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void send_to_rtio_log(struct slice data);
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#define KERNELCPU_EXEC_ADDRESS 0x40800000
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#define KERNELCPU_PAYLOAD_ADDRESS 0x40860000
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#define KERNELCPU_EXEC_ADDRESS 0x45000000
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#define KERNELCPU_PAYLOAD_ADDRESS 0x45060000
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#define KERNELCPU_LAST_ADDRESS 0x4fffffff
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#define KSUPPORT_HEADER_SIZE 0x80
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@ -2,16 +2,16 @@ INCLUDE generated/output_format.ld
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INCLUDE generated/regions.ld
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ENTRY(_reset_handler)
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/* First 4M of main memory are reserved for runtime
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/* First 64M of main memory are reserved for runtime
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* code/data/heap, then comes kernel memory.
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* Next 4M of main memory are reserved for
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* Next 16M of main memory are reserved for
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* the background RPC queue.
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* First 384K of kernel memory are for support code.
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* Support code is loaded at ORIGIN-0x80 so that ELF headers
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* are also loaded.
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*/
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MEMORY {
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ksupport (RWX) : ORIGIN = 0x40800000, LENGTH = 0x60000
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ksupport (RWX) : ORIGIN = 0x45000000, LENGTH = 0x60000
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}
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/* Kernel stack is at the end of main RAM. */
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@ -5,8 +5,8 @@ use board_misoc::{mem, cache};
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const SEND_MAILBOX: *mut usize = (mem::MAILBOX_BASE + 4) as *mut usize;
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const RECV_MAILBOX: *mut usize = (mem::MAILBOX_BASE + 8) as *mut usize;
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const QUEUE_BEGIN: usize = 0x40400000;
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const QUEUE_END: usize = 0x407fff80;
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const QUEUE_BEGIN: usize = 0x44000000;
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const QUEUE_END: usize = 0x44ffff80;
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const QUEUE_CHUNK: usize = 0x1000;
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pub unsafe fn init() {
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@ -1,8 +1,8 @@
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use core::fmt;
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use dyld;
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pub const KERNELCPU_EXEC_ADDRESS: usize = 0x40800000;
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pub const KERNELCPU_PAYLOAD_ADDRESS: usize = 0x40860000;
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pub const KERNELCPU_EXEC_ADDRESS: usize = 0x45000000;
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pub const KERNELCPU_PAYLOAD_ADDRESS: usize = 0x45060000;
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pub const KERNELCPU_LAST_ADDRESS: usize = 0x4fffffff;
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pub const KSUPPORT_HEADER_SIZE: usize = 0x80;
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@ -6,7 +6,7 @@ ENTRY(_reset_handler)
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* ld does not allow this expression here.
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*/
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MEMORY {
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runtime (RWX) : ORIGIN = 0x40000000, LENGTH = 0x400000 /* 4M */
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runtime (RWX) : ORIGIN = 0x40000000, LENGTH = 0x4000000 /* 64M */
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}
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SECTIONS
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@ -7,7 +7,7 @@ from misoc.integration.wb_slaves import WishboneSlaveManager
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class KernelCPU(Module):
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def __init__(self, platform,
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exec_address=0x40800000,
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exec_address=0x45000000,
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main_mem_origin=0x40000000,
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l2_size=8192):
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self._reset = CSRStorage(reset=1)
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