forked from M-Labs/artiq
rtio/sed: rename fifos/gates, refactor tsc
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@ -4,21 +4,21 @@ from migen.genlib.fifo import *
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from artiq.gateware.rtio.sed import layouts
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from artiq.gateware.rtio.sed import layouts
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__all__ = ["FIFO"]
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__all__ = ["FIFOs"]
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class FIFO(Module):
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class FIFOs(Module):
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def __init__(self, lane_count, mode, fifo_depth, layout_payload):
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def __init__(self, lane_count, fifo_depth, layout_payload, mode):
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seqn_width = layouts.seqn_width(lane_count, fifo_width)
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seqn_width = layouts.seqn_width(lane_count, fifo_depth)
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self.input = [layouts.fifo_ingress(seqn_width, layout_payload)
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self.input = [Record(layouts.fifo_ingress(seqn_width, layout_payload))
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for _ in range(lane_count)]
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for _ in range(lane_count)]
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self.output = [layouts.fifo_egress(seqn_width, layout_payload)
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self.output = [Record(layouts.fifo_egress(seqn_width, layout_payload))
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for _ in range(lane_count)]
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for _ in range(lane_count)]
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if mode == "sync":
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if mode == "sync":
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fifo_cls = fifo.SyncFIFOBuffered
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fifo_cls = SyncFIFOBuffered
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elif mode == "async":
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elif mode == "async":
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fifo_cls = fifo.AsyncFIFO
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fifo_cls = AsyncFIFO
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else:
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else:
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raise ValueError
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raise ValueError
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@ -3,10 +3,10 @@ from migen import *
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from artiq.gateware.rtio.sed import layouts
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from artiq.gateware.rtio.sed import layouts
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__all__ = ["TSCGate"]
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__all__ = ["Gates"]
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class TSCGate(Module):
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class Gates(Module):
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def __init__(self, lane_count, seqn_width, layout_fifo_payload, layout_output_network_payload):
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def __init__(self, lane_count, seqn_width, layout_fifo_payload, layout_output_network_payload):
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self.input = [Record(layouts.fifo_egress(seqn_width, layout_fifo_payload))
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self.input = [Record(layouts.fifo_egress(seqn_width, layout_fifo_payload))
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for _ in range(lane_count)]
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for _ in range(lane_count)]
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@ -17,12 +17,11 @@ class TSCGate(Module):
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fine_ts_width = len(self.output[0].fine_ts)
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fine_ts_width = len(self.output[0].fine_ts)
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else:
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else:
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fine_ts_width = 0
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fine_ts_width = 0
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self.tsc = Signal(64-fine_ts_width)
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self.coarse_timestamp = Signal(64-fine_ts_width)
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# # #
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# # #
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self.sync += self.tsc.eq(self.tsc + 1)
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for input, output in zip(self.input, self.output):
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for input, output in zip(self.input, self.output):
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for field, _ in output.payload.layout:
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for field, _ in output.payload.layout:
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if field == "fine_ts":
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if field == "fine_ts":
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@ -32,6 +31,5 @@ class TSCGate(Module):
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self.sync += output.seqn.eq(input.seqn)
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self.sync += output.seqn.eq(input.seqn)
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self.comb += output.replace_occured.eq(0)
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self.comb += output.replace_occured.eq(0)
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self.comb += input.re.eq(input.payload.timestamp[fine_ts_width:] == self.tsc)
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self.comb += input.re.eq(input.payload.timestamp[fine_ts_width:] == self.coarse_timestamp)
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self.sync += ouput.valid.eq(input.re & input.readable)
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self.sync += output.valid.eq(input.re & input.readable)
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