forked from M-Labs/artiq
drtio: fixes
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45621934fd
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929a7650a8
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@ -48,17 +48,18 @@ class IOT(Module):
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# FIFO write
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self.comb += fifo.we.eq(rt_packets.write_stb
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& (rt_packets.write_channel == n))
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self.sync += \
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self.sync += [
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If(rt_packets.write_overflow_ack,
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rt_packets.write_overflow.eq(0)),
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If(rt_packets.write_underflow_ack,
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rt_packets.write_underflow.eq(0)),
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If(fifo.we,
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If(rt_packets.write_overflow_ack,
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rt_packets.write_overflow.eq(0)),
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If(~fifo.writable, rt_packets.write_overflow.eq(1)),
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If(rt_packets.write_underflow_ack,
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rt_packets.write_underflow.eq(0)),
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If(rt_packets.write_timestamp[max_fine_ts_width:] < (tsc + 4),
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rt_packets.write_underflow.eq(1)
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)
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)
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]
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if data_width:
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self.comb += fifo_in.data.eq(rt_packets.write_data)
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if address_width:
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@ -48,7 +48,7 @@ class RTController(Module):
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self.comb += [
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rt_packets.tsc_value.eq(
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self.counter.value_rtio + tsc_correction),
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self.kcsrs.set_time.r.eq(rt_packets.set_time_stb)
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self.kcsrs.set_time.w.eq(rt_packets.set_time_stb)
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]
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self.sync += [
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If(rt_packets.set_time_ack, rt_packets.set_time_stb.eq(0)),
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@ -98,8 +98,7 @@ class RTController(Module):
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cond_sequence_error = self.kcsrs.o_timestamp.storage < last_timestamps.dat_r
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cond_underflow = ((self.kcsrs.o_timestamp.storage[fine_ts_width:]
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- self.kcsrs.underflow_margin.storage[fine_ts_width:]) < self.counter.value_sys)
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cond_fifo_emptied = ((last_timestamps.dat_r[fine_ts_width:]
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< self.counter.value_sys - self.kcsrs.underflow_margin.storage[fine_ts_width:])
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cond_fifo_emptied = ((last_timestamps.dat_r[fine_ts_width:] < self.counter.value_sys)
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& (last_timestamps.dat_r != 0))
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fsm.act("IDLE",
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