forked from M-Labs/artiq
1
0
Fork 0

siphaser: cleanup

This commit is contained in:
Sebastien Bourdeauducq 2018-03-07 11:15:44 +08:00
parent 74d1df3ff0
commit 916197c4d7
5 changed files with 83 additions and 82 deletions

View File

@ -1,6 +1,6 @@
use core::result; use core::result;
use board::clock; use board::clock;
#[cfg(any(not(si5324_soft_reset), has_si_phaser))] #[cfg(not(si5324_soft_reset))]
use board::csr; use board::csr;
use i2c; use i2c;
@ -266,43 +266,44 @@ pub fn select_input(input: Input) -> Result<()> {
Ok(()) Ok(())
} }
#[cfg(has_si_phaser)] #[cfg(has_siphaser)]
pub fn select_recovered_clock(rc: bool) -> Result<()> { pub mod siphaser {
use super::*;
use board::csr;
use board::clock;
pub fn select_recovered_clock(rc: bool) -> Result<()> {
write(3, (read(3)? & 0xdf) | (1 << 5))?; // DHOLD=1 write(3, (read(3)? & 0xdf) | (1 << 5))?; // DHOLD=1
unsafe { unsafe {
csr::si_phaser::switch_clocks_write(if rc { 1 } else { 0 }); csr::siphaser::switch_clocks_write(if rc { 1 } else { 0 });
} }
write(3, (read(3)? & 0xdf) | (0 << 5))?; // DHOLD=0 write(3, (read(3)? & 0xdf) | (0 << 5))?; // DHOLD=0
monitor_lock()?; monitor_lock()?;
Ok(()) Ok(())
} }
#[cfg(has_si_phaser)] fn phase_shift(direction: u8) {
fn phase_shift(direction: u8) {
unsafe { unsafe {
csr::si_phaser::phase_shift_write(direction); csr::siphaser::phase_shift_write(direction);
while csr::si_phaser::phase_shift_done_read() == 0 {} while csr::siphaser::phase_shift_done_read() == 0 {}
} }
// wait for the Si5324 loop to stabilize // wait for the Si5324 loop to stabilize
clock::spin_us(500); clock::spin_us(500);
} }
#[cfg(has_si_phaser)] fn get_phaser_sample() -> bool {
fn get_phaser_sample() -> bool {
let mut sample = true; let mut sample = true;
for _ in 0..32 { for _ in 0..32 {
if unsafe { csr::si_phaser::sample_result_read() } == 0 { if unsafe { csr::siphaser::sample_result_read() } == 0 {
sample = false; sample = false;
} }
} }
sample sample
} }
#[cfg(has_si_phaser)] const PS_MARGIN: u32 = 28;
const PS_MARGIN: u32 = 28;
#[cfg(has_si_phaser)] fn get_stable_phaser_sample() -> (bool, u32) {
fn get_stable_phaser_sample() -> (bool, u32) {
let mut nshifts: u32 = 0; let mut nshifts: u32 = 0;
loop { loop {
let s1 = get_phaser_sample(); let s1 = get_phaser_sample();
@ -323,10 +324,9 @@ fn get_stable_phaser_sample() -> (bool, u32) {
return (s2, nshifts); return (s2, nshifts);
} }
} }
} }
#[cfg(has_si_phaser)] pub fn calibrate_skew(skew: u16) -> Result<()> {
pub fn calibrate_skew(skew: u16) -> Result<()> {
// Get into a 0 region // Get into a 0 region
let (s1, mut nshifts) = get_stable_phaser_sample(); let (s1, mut nshifts) = get_stable_phaser_sample();
if s1 { if s1 {
@ -352,4 +352,5 @@ pub fn calibrate_skew(skew: u16) -> Result<()> {
phase_shift(1); phase_shift(1);
} }
Ok(()) Ok(())
}
} }

View File

@ -235,8 +235,8 @@ fn startup() {
process_errors(); process_errors();
} }
info!("link is up, switching to recovered clock"); info!("link is up, switching to recovered clock");
si5324::select_recovered_clock(true).expect("failed to switch clocks"); si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
si5324::calibrate_skew(32).expect("failed to calibrate skew"); si5324::siphaser::calibrate_skew(32).expect("failed to calibrate skew");
drtio_reset(false); drtio_reset(false);
drtio_reset_phy(false); drtio_reset_phy(false);
while drtio_link_rx_up() { while drtio_link_rx_up() {
@ -246,7 +246,7 @@ fn startup() {
drtio_reset_phy(true); drtio_reset_phy(true);
drtio_reset(true); drtio_reset(true);
info!("link is down, switching to local crystal clock"); info!("link is down, switching to local crystal clock");
si5324::select_recovered_clock(false).expect("failed to switch clocks"); si5324::siphaser::select_recovered_clock(false).expect("failed to switch clocks");
} }
} }

View File

@ -21,7 +21,7 @@ from artiq.gateware.amp import AMPSoC
from artiq.gateware import rtio from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi2 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi2
from artiq.gateware.drtio.transceiver import gtp_7series from artiq.gateware.drtio.transceiver import gtp_7series
from artiq.gateware.drtio.si_phaser import SiPhaser7Series from artiq.gateware.drtio.siphaser import SiPhaser7Series
from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
from artiq.build_soc import build_artiq_soc from artiq.build_soc import build_artiq_soc
@ -574,11 +574,11 @@ class Satellite(BaseSoC):
self.add_memory_group("drtio_aux", ["drtio0_aux"]) self.add_memory_group("drtio_aux", ["drtio0_aux"])
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
self.submodules.si_phaser = SiPhaser7Series( self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"), si5324_clkin=platform.request("si5324_clkin"),
si5324_clkout_fabric=platform.request("si5324_clkout_fabric") si5324_clkout_fabric=platform.request("si5324_clkout_fabric")
) )
self.csr_devices.append("si_phaser") self.csr_devices.append("siphaser")
i2c = self.platform.request("i2c") i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c") self.csr_devices.append("i2c")

View File

@ -33,7 +33,7 @@ from artiq.gateware import remote_csr
from artiq.gateware import rtio from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple, sawg from artiq.gateware.rtio.phy import ttl_simple, sawg
from artiq.gateware.drtio.transceiver import gth_ultrascale from artiq.gateware.drtio.transceiver import gth_ultrascale
from artiq.gateware.drtio.si_phaser import SiPhaser7Series from artiq.gateware.drtio.siphaser import SiPhaser7Series
from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
from artiq.build_soc import build_artiq_soc from artiq.build_soc import build_artiq_soc
@ -433,13 +433,13 @@ class Satellite(BaseSoC):
self.add_memory_group("drtio_aux", ["drtio0_aux"]) self.add_memory_group("drtio_aux", ["drtio0_aux"])
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
self.submodules.si_phaser = SiPhaser7Series( self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"), si5324_clkin=platform.request("si5324_clkin"),
si5324_clkout_fabric=platform.request("si5324_clkout_fabric") si5324_clkout_fabric=platform.request("si5324_clkout_fabric")
) )
platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]", platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]",
mmcm_ps=self.si_phaser.mmcm_ps_output) mmcm_ps=self.siphaser.mmcm_ps_output)
self.csr_devices.append("si_phaser") self.csr_devices.append("siphaser")
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n") self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c") i2c = self.platform.request("i2c")