siphaser: cleanup

artiq/firmware/libboard_artiq/si5324.rs

@@ -1,6 +1,6 @@
 use core::result;
 use board::clock;
-#[cfg(any(not(si5324_soft_reset), has_si_phaser))]
+#[cfg(not(si5324_soft_reset))]
 use board::csr;
 use i2c;
 
@@ -266,42 +266,43 @@ pub fn select_input(input: Input) -> Result<()> {
     Ok(())
 }
 
-#[cfg(has_si_phaser)]
+#[cfg(has_siphaser)]
+pub mod siphaser {
+    use super::*;
+    use board::csr;
+    use board::clock;
+
     pub fn select_recovered_clock(rc: bool) -> Result<()> {
         write(3,   (read(3)? & 0xdf) | (1 << 5))?;  // DHOLD=1
         unsafe {
-        csr::si_phaser::switch_clocks_write(if rc { 1 } else { 0 });
+            csr::siphaser::switch_clocks_write(if rc { 1 } else { 0 });
         }
         write(3,   (read(3)? & 0xdf) | (0 << 5))?;  // DHOLD=0
         monitor_lock()?;
         Ok(())
     }
 
-#[cfg(has_si_phaser)]
     fn phase_shift(direction: u8) {
         unsafe {
-        csr::si_phaser::phase_shift_write(direction);
+            csr::siphaser::phase_shift_write(direction);
-        while csr::si_phaser::phase_shift_done_read() == 0 {}
+            while csr::siphaser::phase_shift_done_read() == 0 {}
         }
         // wait for the Si5324 loop to stabilize
         clock::spin_us(500);
     }
 
-#[cfg(has_si_phaser)]
     fn get_phaser_sample() -> bool {
         let mut sample = true;
         for _ in 0..32 {
-        if unsafe { csr::si_phaser::sample_result_read() } == 0 {
+            if unsafe { csr::siphaser::sample_result_read() } == 0 {
                 sample = false;
             }
         }
         sample
     }
 
-#[cfg(has_si_phaser)]
     const PS_MARGIN: u32 = 28;
 
-#[cfg(has_si_phaser)]
     fn get_stable_phaser_sample() -> (bool, u32) {
         let mut nshifts: u32 = 0;
         loop {
@@ -325,7 +326,6 @@ fn get_stable_phaser_sample() -> (bool, u32) {
         }
     }
 
-#[cfg(has_si_phaser)]
     pub fn calibrate_skew(skew: u16) -> Result<()> {
         // Get into a 0 region
         let (s1, mut nshifts) = get_stable_phaser_sample();
@@ -353,3 +353,4 @@ pub fn calibrate_skew(skew: u16) -> Result<()> {
         }
         Ok(())
     }
+}

artiq/firmware/satman/main.rs

@@ -235,8 +235,8 @@ fn startup() {
             process_errors();
         }
         info!("link is up, switching to recovered clock");
-        si5324::select_recovered_clock(true).expect("failed to switch clocks");
+        si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
-        si5324::calibrate_skew(32).expect("failed to calibrate skew");
+        si5324::siphaser::calibrate_skew(32).expect("failed to calibrate skew");
         drtio_reset(false);
         drtio_reset_phy(false);
         while drtio_link_rx_up() {
@@ -246,7 +246,7 @@ fn startup() {
         drtio_reset_phy(true);
         drtio_reset(true);
         info!("link is down, switching to local crystal clock");
-        si5324::select_recovered_clock(false).expect("failed to switch clocks");
+        si5324::siphaser::select_recovered_clock(false).expect("failed to switch clocks");
     }
 }
 

artiq/gateware/targets/kasli.py

@@ -21,7 +21,7 @@ from artiq.gateware.amp import AMPSoC
 from artiq.gateware import rtio
 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi2
 from artiq.gateware.drtio.transceiver import gtp_7series
-from artiq.gateware.drtio.si_phaser import SiPhaser7Series
+from artiq.gateware.drtio.siphaser import SiPhaser7Series
 from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
 from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
 from artiq.build_soc import build_artiq_soc
@@ -574,11 +574,11 @@ class Satellite(BaseSoC):
         self.add_memory_group("drtio_aux", ["drtio0_aux"])
 
         self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
-        self.submodules.si_phaser = SiPhaser7Series(
+        self.submodules.siphaser = SiPhaser7Series(
             si5324_clkin=platform.request("si5324_clkin"),
             si5324_clkout_fabric=platform.request("si5324_clkout_fabric")
         )
-        self.csr_devices.append("si_phaser")
+        self.csr_devices.append("siphaser")
         i2c = self.platform.request("i2c")
         self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
         self.csr_devices.append("i2c")

artiq/gateware/targets/sayma_amc.py

@@ -33,7 +33,7 @@ from artiq.gateware import remote_csr
 from artiq.gateware import rtio
 from artiq.gateware.rtio.phy import ttl_simple, sawg
 from artiq.gateware.drtio.transceiver import gth_ultrascale
-from artiq.gateware.drtio.si_phaser import SiPhaser7Series
+from artiq.gateware.drtio.siphaser import SiPhaser7Series
 from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
 from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
 from artiq.build_soc import build_artiq_soc
@@ -433,13 +433,13 @@ class Satellite(BaseSoC):
         self.add_memory_group("drtio_aux", ["drtio0_aux"])
 
         self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
-        self.submodules.si_phaser = SiPhaser7Series(
+        self.submodules.siphaser = SiPhaser7Series(
             si5324_clkin=platform.request("si5324_clkin"),
             si5324_clkout_fabric=platform.request("si5324_clkout_fabric")
         )
         platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]",
-            mmcm_ps=self.si_phaser.mmcm_ps_output)
+            mmcm_ps=self.siphaser.mmcm_ps_output)
-        self.csr_devices.append("si_phaser")
+        self.csr_devices.append("siphaser")
         self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
         self.csr_devices.append("si5324_rst_n")
         i2c = self.platform.request("i2c")