From 9142a5ab8ad3e03d6f869bc7d350b8478033ee68 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 20 Jun 2018 17:39:43 +0800 Subject: [PATCH] rtio: expose coarse timestamp in RTIO and DRTIO satellite cores --- artiq/gateware/drtio/core.py | 1 + artiq/gateware/rtio/core.py | 1 + 2 files changed, 2 insertions(+) diff --git a/artiq/gateware/drtio/core.py b/artiq/gateware/drtio/core.py index ff64bf5f0..61c1d2eb4 100644 --- a/artiq/gateware/drtio/core.py +++ b/artiq/gateware/drtio/core.py @@ -90,6 +90,7 @@ class DRTIOSatellite(Module): coarse_ts.eq(coarse_ts + 1) ) self.comb += self.rt_packet.cri.counter.eq(coarse_ts << fine_ts_width) + self.coarse_ts = coarse_ts self.submodules.outputs = ClockDomainsRenamer("rio")( SED(channels, fine_ts_width, "sync", diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py index 484c64bbe..edab0bf08 100644 --- a/artiq/gateware/rtio/core.py +++ b/artiq/gateware/rtio/core.py @@ -73,6 +73,7 @@ class Core(Module, AutoCSR): coarse_ts_cdc.i.eq(coarse_ts), self.cri.counter.eq(coarse_ts_cdc.o << glbl_fine_ts_width) ] + self.coarse_ts = coarse_ts # Outputs/Inputs quash_channels = [n for n, c in enumerate(channels) if isinstance(c, LogChannel)]